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HARRIS
888-9058-001
WARNING: Disconnect and lockout AC primary power prior to servicing
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5.5.1.12 Interlocks (Sheet 12)
The External, Failsafe and Phase loss interlocks are isolated by opto-coupler. A spare is
also available for use in custom systems.
The external interlock is a series system of switches, a complete set of closed switches
complete the interlock. The external interlock is connected to 1A7TB1 terminals one
and two. 1A7TB1 connects to J11 by wiring harness. In a similar manner, the Failsafe
interlock connects to 1A7TB1 terminals three and four. Any interlock not used requires
a jumper wire to complete the interlock.
5.5.1.13 Peak Detectors (Sheets 13 and 14)
NOTE:
This control system is designed for both analog and digital service, the analog
visual circuits are used for the digital signal path. Visual Forward becomes Digital
Forward, Visual Reflected becomes Digital Reflected and no Aural circuitry is
used in the digital cabinet version.
Each channel of peak detection is actually composed of two identical detectors, the RF
input is connected to one detector, the other is only connected to ground. Each detector
diode output voltage is a function of RF input and diode temperature. The top diode has
an output voltage that changes with RF input and temperature. The lower diode output
is only changes with temperature. After opamp unity gain buffering, the two voltages
are inputs to the following differential amplifier, the output of this is the difference of
the two voltages representing the RF input voltage only. This circuit is designed for
three volt at the test point at maximum input RF voltage. This voltage will be used with
a lookup table in software to correct for the diode nonlinearity. This uncorrected voltage
is also available at the remote interface as “Raw Visual Forward”. Reflected and reject
loads are metered with similar circuitry.
5.5.1.14 Fault Detection (Sheet 15)
Digital system power output peak detector DC voltage (VIS_FWD_PWR), the + input
to the comparator U60 is compared with a DC voltage from the wiper of a digital pot.
This pot is part of U83, a quad digitally controlled potentiometer. The SO, serial output
pin allows the microprocessor to read the wiper position. The SI is the serial data input
pin, serial data into this pin changes the wiper position. SCK is the serial clock for the
SPI bus. CS is the chip select pin, microprocessor pulls this pin low to select the chip.
The high terminal is connected to the 4.096 volt reference and the low terminal is
connected to ground. The microprocessor addresses this pot, then sets the resistor wiper
setting. This voltage divider generates the inverting input voltage for the comparator,
determining the comparator change point. When the power is below the set point of
80% of nominal, the forward power fault is generated (VIS_FWD_FLT). This will
generate a WARNING type fault.
