GE C70, Instruction Manual

Page: 90 / 708

3-32 C70 Capacitor Bank Protection and Control System GE Multilin
3.3 DIRECT INPUT/OUTPUT COMMUNICATIONS 3 HARDWARE
3
Figure 3–37: TIMING CONFIGURATION FOR RS422 TWO-CHANNEL, THREE-TERMINAL APPLICATION
Data module 1 provides timing to the C70 RS422 interface via the ST(A) and ST(B) outputs. Data module 1 also provides
timing to data module 2 TT(A) and TT(B) inputs via the ST(A) and AT(B) outputs. The data module pin numbers have been
omitted in the figure above since they vary by manufacturer.
c) TRANSMIT TIMING
The RS422 interface accepts one clock input for transmit timing. It is important that the rising edge of the 64 kHz transmit
timing clock of the multiplexer interface is sampling the data in the center of the transmit data window. Therefore, it is impor-
tant to confirm clock and data transitions to ensure proper system operation. For example, the following figure shows the
positive edge of the Tx clock in the center of the Tx data bit.
Figure 3–38: CLOCK AND DATA TRANSITIONS
Data module 1
Data module 2
Signal name
Signal name
SD(A) - Send data
TT(A) - Terminal timing
TT(B) - Terminal timing
SD(B) - Send data
RD(A) - Received data
RD(A) - Received data
SD(A) - Send data
SD(B) - Send data
RD(B) - Received data
RD(B) - Received data
RS(A) - Request to send (RTS)
RS(A) - Request to send (RTS)
RT(A) - Receive timing
CS(A) - Clear To send
CS(A) - Clear To send
RT(B) - Receive timing
CS(B) - Clear To send
CS(B) - Clear To send
Local loopback
Local loopback
Remote loopback
Remote loopback
Signal ground
Signal ground
ST(A) - Send timing
ST(A) - Send timing
ST(B) - Send timing
ST(B) - Send timing
RS(B) - Request to send (RTS)
RS(B) - Request to send (RTS)
831022A3.CDR
W 7a
W 2b
W 8a
7W
Shld.
Shld.
Tx1(+)
Tx2(+)
Tx1(-)
Tx2(-)
Rx1(+)
Rx2(+)
+
com
Rx1(-)
Rx2(-)
–
INTER-REL
A
Y
C
OMMUNICA
TIONS
W 3a
W 5b
W 5a
W 3b
W 2a
W 6a
W 6b
W 7b
W 8b
W 4b
W 4a
RS422
CHANNEL 1
RS422
CHANNEL 2
CLOCK
SURGE
831733A1.CDR
Tx Clock
Tx Data