CHAPTER 9: THEORY OF OPERATION
OVERVIEW
L60 LINE PHASE COMPARISON SYSTEM – INSTRUCTION MANUAL
9-31
9
Figure 9-24: Permissive dual-comparison scheme logic through fault condition
The external fault behind one relay with a blocking scheme in a dual-breaker application results in transmittal of the
continuous blocking signal to the remote terminal.
The received pulses can be distorted in a number of ways. Some of those distortions must be filtered out, and some of
them are left as received (their rectification is neither necessary nor safe).
The receive information is delivered from the carrier or other receiver as a DC voltage. In prior generations of relays, the
input for this signal was a binary or status circuit that reported only a debounced or filtered true or false indication to the
following circuits or microprocessor. In the newest design, this signal is sampled synchronously with the local AC signals
through the same A/D converter controlled from the same S&H signal, and at the same high sampling rate. In this way,
both the pieces of information (local AC currents, and remote phase signals) are automatically aligned in time, and the
analog value of the receiver output status signal can be utilized to achieve the closest approach to the core phase
comparison operating principles.
The first and obvious distortion in the received signal is a time delay added by the communication channel. This must be
corrected by buffering the pulses to be aligned for time differentials with respect to the slowest remote channel. Digital
technology means that such delays can be used in a precise and straightforward way by buffering the signal sample
values in a delay queue. Analog technologies can have difficulties in precisely delaying those signals, particularly if those
signals are of variable length and have other impairments.
The second possible distortion is high frequency noise embedded on the mark or space pulses. These are left unaltered.
The receiving relay does not have any reliable information as to the real value of the received information, and therefore is
not to alter it based on any assumptions. The phase comparison algorithm has a well-understood security margin due to
the averaging action of the trip integrators. The integrators deal with this kind of noise, yielding a predictable response that
is transparent and easy to grasp by the user.
The third type of distortion is pulse asymmetry. Modern carrier sets claim to be free of this problem, but historically it has
been observed that either the mark or the space signals were extended at the receiving end compared with the originally
sent signal. Distinction between the delay and asymmetry is relatively straightforward: if the rising edges and the falling
831805A1.CDR
F1-IA
F2-IB
F3-IC
M1-IA
M2-IB
M3-IC
87PC BKR 1 CURRENT
87PC BKR2 CURRENT
BKR1 POS
BKR 1 FDL
BKR2 POS
BKR2 FDL
BKR 1 NEG
BKR2 NEG
POS
NEG
FDL
TX POS
TX NEG
1) CB1 currents in the forward direction
on the breaker-and-a-half diameter.
2) CB2 currents in the reverse direction;
signs of shallow CT saturation (DC
component eliminated, “tail” after the
fault is cleared).
3) Composite signals of different
magnitudes but out-of-phase.
4) CB1 produces individual pulses;
FDL picks up.
5) CB2 pulses are out-of-phase;
FDL picks up.
6) Dual breaker logic effectively erases
both positive and negative pulses.
7) FDL transmits for both breaker pickups.
8) Transmitted pulses are very short (almost
perfectly erased); no 87PC operation.
87PC OP
