9-28
L60 LINE PHASE COMPARISON SYSTEM – INSTRUCTION MANUAL
OVERVIEW
CHAPTER 9: THEORY OF OPERATION
9
The quadrature component of the signal is needed to estimate magnitude of the input current for fault detectors:
Eq. 9-3
Two levels of fast overcurrent supervision are required: fault detection low (FDL) for keying and fault detection high (FDH)
for tripping. These conditions are supervisory; therefore, they do not have to be very accurate. Instead, they need to be fast
enough not to slow the remainder of the 87PC algorithm.
The fast magnitude is calculated as:
Eq. 9-4
Figure 9-21: Example of mixing current operation (relay COMTRADE record)
The response of the overcurrent condition to switch off transients, including current reversal on parallel lines and heavily
saturated CTs, is important. The key design requirement is to keep the FDL and FDH picked up and resetting in a way that
ensures both dependability and security in both tripping and blocking arrangements.
From this perspective, to boost the magnitude on heavily saturated CTs, the RMS component is calculated as follows (on a
sample-by-sample basis):
Eq. 9-5
where N
1
represents the number of samples per cycle (64).
The magnitude estimator combines the fast estimator for accuracy, the RMS value for dependability on CT saturation or
other severe transients, and the waveform peak for speed:
Eq. 9-6
The local operating current is converted into phase pulses. It is important to realize that the operation is nonlinear, erasing
almost all information contained in the magnitude of the signal and presenting exclusively the phase information by
encoding the on/off pulses signifying polarity of the operating signal. This polarity is preserved with respect to the universal
analog time. This is one of the key advantages of the phase comparison principle, even when implemented digitally: no
synchronization is required between the individual relays of the 87PC scheme.
The raw LOC-al pulses (Positive and Negative polarity) are produced disregarding the FDL and FDH flags. The fault detector
flags are used in the dual-breaker, key, and trip logic. The raw pulses are calculated as follows.
i
MIX_Q
1
3
-- i
Q_A
1 K
–
(
)
1
2
-- K 1
–
(
)
i
Q_B
i
Q_C
+
(
)
3
2
------ K 1
+
(
)
i
D_C
i
D_B
–
(
)
+
+
=
I
FAST
i
MIX
(
)
2
I
MIX_Q
(
)
2
+
=
F1-IA
F2-IB
F2-IC
87PC BKR1 current
1) Internal AG fault tripped single-pole.
2) Followed by the second interval
BG fault during the single-pole open condition
831802A1.CDR
3) Composite signal (negative-sequence) of the 87PC function
I
RMS k
( )
2
N
1
------
I
MIX k p
–
(
)
(
)
2
p
0
=
N
1
1
–
=
I
AUX
max I
RMS
I
FAST
0.85 abs i
MIX
(
)
×
,
,
(
)
=
