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CHAPTER 2 CPU

2.1

CPU Architecture

The FR30 CPU is a high performance core that uses the RISC architecture and
supports advanced functional instructions geared to embedding applications.

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Characteristics of CPU Architecture

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RISC architecture

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Basic instruction: One instruction per cycle

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32-bit architecture

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32-bit general-purpose register x 16

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Linear 4-gigabyte memory space

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Internal operation of the adder

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Addition of 32 bits x 32 bits: Five cycles

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Addition of 16 bits x 16 bits: Three cycles

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Enhanced interrupt processing function

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High-speed response (six cycles)

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Support of multiple concurrent interrupts

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Level mask function (16 levels)

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Enhanced I/O operation instructions

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Inter-memory transfer instruction

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Bit processing instruction

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High coding efficiency

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Basic instruction word length: 16 bits

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Low power consumption

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Sleep mode and stop mode

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Summary of Contents for MB91F109

Page 1: ...FUJITSU SEMICONDUCTOR CONTROLLER MANUAL FR30 32 Bit Microcontroller MB91F109 Hardware Manual CM71 10106 1E ...

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Page 3: ...FUJITSU LIMITED FR30 32 Bit Microcontroller MB91F109 Hardware Manual ...

Page 4: ......

Page 5: ...dding applications that require high CPU processing power This manual explains the functions and operations of the MB91F109 for the engineers who actually develop products using the MB91F109 Read this manual thoroughly Refer to the instruction manual for details on individual instructions Trademarks FR stands for FUJITSU RISC controller a product of Fujitsu Limited Embedded AlgorithmTM is a tradem...

Page 6: ...apter 7 Delayed Interrupt Module Chapter 7 provides an overview of the delayed interrupt module explains the register configuration and functions and operations of the delayed interrupt module Chapter 8 Interrupt Controller Chapter 8 provides an overview of the interrupt controller explains the register configuration and functions and operations of the interrupt controller The chapter also explain...

Page 7: ...explains the flash memory functions and operations The chapter provides information on using the flash memory from the FR CPU For information on using the flash memory from the ROM writer refer to the user s guide for the ROM writer Appendix The appendix provides information on I O maps interrupt vectors terminal states in each CPU status notes on using the little endian area and a listing of inst...

Page 8: ...of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage or where extremely high levels of reliability are demanded such as aerospace systems atomic energy controls sea floor repeaters vehicle operating controls medical devices for life support etc are requested to consult with FUJITSU sales representati...

Page 9: ... via an adapter Various I O ports the clock generator and interrupt controller are connected to the R BUS Since the R BUS is 16 bits wide in which addresses and data are multiplexed it takes twice as much or more cycle time than usual for the CPU to access these resources E unit Operation executing unit φ System clock output from the clock generator to each internal resource connected to the R BUS...

Page 10: ...vi ...

Page 11: ...ts 48 2 7 2 Branch Instructions without Delay Slots 51 2 8 EIT Exception Interrupt and Trap 52 2 8 1 EIT Interrupt Levels 54 2 8 2 Interrupt Control Register ICR 56 2 8 3 System Stack Pointer SSP 57 2 8 4 Interrupt Stack 58 2 8 5 Table Base Register TBR 59 2 8 6 EIT Vector Table 60 2 8 7 Multiple EIT Processing 62 2 8 8 EIT Operation 64 2 9 Reset Sequence 68 2 10 Operation Mode 69 CHAPTER 3 CLOCK ...

Page 12: ...er 0 EPCR0 132 4 13 External Pin Control Register 1 EPCR1 135 4 14 DRAM Signal Control Register DSCR 136 4 15 Little Endian Register LER 138 4 16 Relationship between Data Bus Widths and Control Signals 139 4 16 1 Bus Access with Big Endians 141 4 16 2 Bus Access with Little Endians 147 4 16 3 External Access 151 4 16 4 DRAM Relationships 155 4 17 Bus Timing 159 4 17 1 Basic Read Cycle 162 4 17 2 ...

Page 13: ...uest Levels 217 6 7 Nonmaskable Interrupt NMI Operation 218 CHAPTER 7 DELAYED INTERRUPT MODULE 219 7 1 Overview of Delayed Interrupt Module 220 7 2 Delayed Interrupt Control Register DICR 221 7 3 Operation of Delayed Interrupt Module 222 CHAPTER 8 INTERRUPT CONTROLLER 223 8 1 Overview of Interrupt Controller 224 8 2 Interrupt Controller Block Diagram 227 8 3 Interrupt Control Register ICR 228 8 4 ...

Page 14: ... TMR and 16 Bit Reload Register TMRLR 286 12 4 Operation of 16 Bit Reload Timer 287 12 5 Counter States 289 CHAPTER 13 BIT SEARCH MODULE 291 13 1 Overview of the Bit Search Module 292 13 2 Bit Search Module Registers 293 13 3 Bit Search Module Operation and Save Restore Processing 295 CHAPTER 14 PWM TIMER 299 14 1 Overview of PWM Timer 300 14 2 PWM Timer Block Diagram 302 14 3 Control Status Regis...

Page 15: ...16 1 Outline of Flash Memory 352 16 2 Block Diagram of Flash Memory 354 16 3 Flash Memory Status Register FSTR 355 16 4 Sector Configuration of Flash Memory 357 16 5 Flash Memory Access Modes 359 16 6 Starting the Automatic Algorithm 361 16 7 Execution Status of the Automatic Algorithm 364 APPENDIX 369 APPENDIX A I O Maps 370 APPENDIX B Interrupt Vectors 379 APPENDIX C Pin Status for Each CPU Stat...

Page 16: ...Configuration of Special Registers 36 Figure 2 4 1 Data Mapping in Bit Ordering Mode 42 Figure 2 4 2 Data Mapping in Byte Ordering Mode 42 Figure 2 6 1 MB91F109 Memory Map 44 Figure 2 6 2 Memory Map Common to the FR Series 45 Figure 2 8 1 Example of Interrupt Stack 58 Figure 2 8 2 Example of Multiple EIT Processing 63 Figure 2 10 1 Mode Register Configuration 70 Figure 3 1 1 Clock Generator and Co...

Page 17: ...ernal Register and External Data Bus for Half word Access 148 Figure 4 16 13 Relationship between Internal Register and External Data Bus for Byte Access 148 Figure 4 16 14 Relationship between Internal Register and External Data Bus for 16 bit Bus Width 149 Figure 4 16 15 Relationship between Internal Register and External Data Bus for 8 bit Bus Width 149 Figure 4 16 16 Example of Connection betw...

Page 18: ... High Speed Page Mode 184 Figure 4 17 29 Example of Single DRAM Interface Read Timing Chart 185 Figure 4 17 30 Example of Single DRAM Interface Write Timing Chart 186 Figure 4 17 31 Example of Single DRAM Interface Timing Chart 187 Figure 4 17 32 Example of Hyper DRAM Interface Read Timing Chart 188 Figure 4 17 33 Example of Hyper DRAM Interface Write Timing Chart 189 Figure 4 17 34 Example of Hyp...

Page 19: ...gure 10 9 1 ORE FRE and RDRF Set Timing Mode 0 260 Figure 10 9 2 ORE FRE and RDRF Set Timing Mode 1 261 Figure 10 9 3 ORE and RDRF Set Timing Mode 2 261 Figure 10 9 4 TDRE Set Timing Mode 0 or 1 262 Figure 10 9 5 TDRE Set Timing Mode 2 262 Figure 10 10 1 Sample System Structure for Mode 1 263 Figure 10 10 2 Communication Flowchart for Mode 1 264 Figure 11 1 1 A D Converter Registers 268 Figure 11 ...

Page 20: ...rmal Polarity 319 Figure 14 12 1 Example of Keeping PWM Output at a Lower Level 320 Figure 14 12 2 Example of Keeping PWM Output at a High Level 320 Figure 15 1 1 DMAC Registers 324 Figure 15 1 2 DMAC Block Diagram 325 Figure 16 1 1 Flash Memory Registers 352 Figure 16 2 1 Block diagram of the Flash Memory 354 Figure 16 4 1 Memory Map and Sector Configuration 357 Figure 16 7 1 Structure of the Har...

Page 21: ...Table 3 6 2 Peripheral Machine Clock 83 Table 3 7 1 Watchdog Timer Cycles Specified by WT1 and WT0 85 Table 3 10 1 Types of Operation in Standby Mode 90 Table 3 14 1 Operating Frequency Combinations Depending on whether the Clock Doubler Function is Enabled or Disabled 107 Table 4 3 1 Correspondence between Chip Select Areas and Selectable Bus Interfaces 116 Table 4 10 1 Page Size of DRAM Connecte...

Page 22: ... 1 Selection of the Count Clock 305 Table 14 3 2 PWM Output When 1 is Written to PGMS 305 Table 14 3 3 Selection of Trigger Input Edge 305 Table 14 3 4 Selection of Interrupt Causes 306 Table 14 3 5 Specification of the Polarity of the PWM Output and the Edge 306 Table 14 7 1 Selection of Ch3 Trigger Input 312 Table 14 7 2 Selection of Ch2 Trigger Input 312 Table 14 7 3 Selection of Ch1 Trigger In...

Page 23: ...ons 411 Table E 1 4 Bit Operation Instructions 411 Table E 1 5 Multiplication and Division Instructions 412 Table E 1 6 Shift Instructions 412 Table E 1 7 Immediate Value Setting or 16 32 Bit Immediate Value Transfer Instruction 413 Table E 1 8 Memory Load Instructions 413 Table E 1 9 Memory Store Instructions 414 Table E 1 10 Interregister Transfer Instructions 414 Table E 1 11 Standard Branch Wi...

Page 24: ...xx ...

Page 25: ...1F109 including its characteristics block diagram and function overview 1 1 MB91F109 Characteristics 1 2 General Block Diagram of MB91F109 1 3 Outside Dimensions 1 4 Pin Arrangement Diagrams 1 5 Pin Functions 1 6 I O Circuit Format 1 7 Memory Address Space 1 8 Handling of Devices ...

Page 26: ...gth instructions basic instructions one instruction per cycle Inter memory transfer bit processing and barrel shift instructions which are suitable for embedding applications Function entry exit instructions and register data multiload store instructions which are compliant with high level language instructions Register interlock function which eases assembler coding Branch instruction with delay ...

Page 27: ...se External terminal or internal resource interrupt request Transfer sequence Step transfer or block transfer Burst transfer or continuous transfer Transfer data length Selectable from 8 16 and 32 bits A temporary stop is enabled by an NMI interrupt request UART Independent three channels Full duplex double buffer Data length 7 to 9 bits no parity or 6 to 8 bits with parity Choice between asynchro...

Page 28: ...INT0 to INT3 Internal interrupt causes UART DMAC A D reload timer PWM UTIMER and delayed interrupt Up to 16 priority levels are programmable for interrupts other than nonmaskable interrupts Reset types Power on reset watchdog timer reset software reset and external reset Power save mode Sleep stop mode Clock control Gear function Desired operating clock frequencies can be set for the CPU and perip...

Page 29: ...5 1 1 MB91F109 Characteristics Available Types MB91V106 MB91106 MB91F109 IROM 63 Kbyte IRAM 64 Kbyte CROM 64 Kbyte 254 Kbyte CRAM 64 Kbyte 2 Kbyte RAM 2 Kbyte 2 Kbyte 2 Kbyte I Others ...

Page 30: ... RAS0 RAS1 CS0L CS1L EOP0 EOP1 EOP2 16bit FLASH ROM 254KB RSTX INT0 INT3 NMIX AN0 AN3 AVCC AVRH D31 D16 A24 A00 RDX WR0X 1X D bus 32bit RDY CLK BRQ BGRNTX CS0X 5X DREQ0 DREQ1 DREQ2 DACK0 DACK1 DACK2 32bit CS0H CS1H DW0X DW1X X0 X1 R bus 16bit SC0 SC1 SC2 SO0 SO1 SO2 withBaudRateTimer AVSS AVRL SI0 SI1 SI2 UART 3ch 10bitA DConverter 4ch PWM Timer 4ch Reload Timer 3 ch Port ATGX OCPA0 OCPA3 TRG0 3 R...

Page 31: ...rt 12 35 486 REF 16 30 0 40 642 016 0 05 002 MIN STAND OFF 0 15 0 05 006 002 INDEX 17 90 0 40 14 00 0 20 551 008 705 016 0 13 005 M 18 85 742 REF 22 30 0 40 878 016 1 30 31 50 51 80 81 100 0 25 010 0 0 012 0 65 0256 TYP 0 30 0 10 012 004 LEAD No 0 80 0 20 031 008 3 35 132 MAX Mounting height EIAJ code Plastic QFP with 100 pins Lead pitch Package width x length Lead shape Gull wing Sealing Plastic ...

Page 32: ...03 0 03 0 08 0 18 INDEX 0 10 004 0 08 003 M 059 004 008 0 10 0 20 1 50 005 001 002 0 02 0 05 0 127 15 00 12 00 472 REF 591 NOM A 25 1 100 75 51 50 0 50 0 20 020 008 Details of A part 0 40 016 MAX 0 15 006 MAX 0 15 006 0 15 006 0 10 0 10 004 004 STAND OFF 010 LEAD No Mouting height EIAJ code Plastic LQFP with 100 pins Lead pitch Package width x length Lead shape Gull wing Sealing Plastic mold 0 50 ...

Page 33: ...4 SQ 049 004 008 0 10 0 20 1 25 Mounting height 0 38 0 10 015 004 Stand off 0 10 004 C0 80 031 INDEX 8 00 314 REF 0 80 031 TYP 1 2 4 5 8 10 11 J H G F E D C B A 112 0 45 0 10 112 018 004 M 0 08 003 Plastic FBGA with 112 pins Ball pitch Ball matrix Package width x length Sealing Plastic mold Mount height Ball size Plastic FBGA with 112 pins Note The actual corner shape may differ from the drawing L...

Page 34: ...CK1 PE7 DACK0 PE6 DREQ1 PE5 DREQ0 PE4 INT3 PE3 SC2 INT2 PE2 SC1 VSS X1 X0 VCC INT1 PE1 INT0 PE0 RAS0 PB0 A08 P50 A06 P46 A07 P47 A05 P45 A09 P51 A10 P52 A11 P53 A12 P54 A13 P55 A14 P56 A15 P57 A16 P60 A17 P61 A18 P62 A19 P63 A20 P64 A21 P65 VSS A22 P66 A23 P67 A24 EOP0 P70 AVCC AVRH AVSS AVRL AN0 AN1 AN2 SO0 PF1 TRG1 SI0 PF0 TRG0 AN3 P20 D16 P21 D17 P22 D18 P85 WR1X P84 WR0X P83 RDX P82 BRQ P81 BG...

Page 35: ...F4 TRG3 SI2 PF5 OCPA1 SO2 PF6 OCPA2 PF7 OCPA0 ATGX DACK1 PE7 DACK0 PE6 DREQ1 PE5 DREQ0 PE4 INT3 PE3 SC2 INT2 PE2 SC1 VSS X1 X0 VCC INT1 PE1 INT0 PE0 RAS0 PB0 CS0L PB1 CS0H PB2 DW0X PB3 RAS1 PB4 EOP2 SI0 PF0 TRG0 P47 A07 P46 A06 P45 A05 P44 A04 P43 A03 P42 A02 P41 A01 VCC P40 A00 P37 D31 VSS P36 D30 P35 D29 P34 D28 P33 D27 P32 D26 P31 D25 P30 D24 P27 D23 P26 D22 P25 D21 P24 D20 P23 D19 P22 D18 P21 ...

Page 36: ...TER 1 OVERVIEW Pin Arrangements FBGA 112 Figure 1 4 3 FBGA 112 Pin Arrangements Table 1 4 1 shows the cross references of the FBGA package pin names L K J H G F E D C B A 1 2 3 4 5 6 7 8 10 9 11 TOP VIEW INDEX ...

Page 37: ... J10 J11 K1 A06 P46 A12 P54 A11 P53 N C D16 P20 B5 B6 B7 B8 B9 X0 INT2 SC1 PE2 DACK0 PE6 SO2 OPCA2 PF6 SI1 TRG2 PF3 F2 F3 F4 F8 F9 VSS MD0 MD2 A24 P70 EOP0 VSS K2 K3 K4 K5 K6 D18 P22 D20 P24 D23 P27 D27 P33 D30 P36 B10 B11 C1 C2 C3 SO0 TRG1 PF1 AN3 DW1X PB7 VCC CLK PA6 F10 F11 G1 G2 G3 A21 P65 A20 P64 N C MD1 RDY P80 K7 K8 K9 K10 K11 A00 P40 A02 P42 A05 P45 A10 P52 A09 P51 C4 C5 C6 C7 C8 DW0X PB3 ...

Page 38: ...e external bus width is set to 8 bits or in single chip mode these pins can be used as general purpose I O ports P20 to P27 9 10 11 12 13 14 15 16 D24 P30 D25 P31 D26 P32 D27 P33 D28 P34 D29 P35 D30 P36 D31 P37 E Bits 24 to 31 of external data bus When these pins are not used for the data bus they can be used as general purpose I O ports P30 to P37 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 A...

Page 39: ...DY P80 E External Ready input 0 is input when the bus cycle being executed is not completed When the pin is not used for this purpose it can be used as a general purpose I O port 43 BGRNTX P81 F Output of external bus release acceptance L is output when the external bus has been released When the pin is not used for this purpose it can be used as a general purpose I O port 44 BRQ P82 E Input of ex...

Page 40: ... This function is valid when DMAC EOP output is enabled PA3 When CS3X and EOP1 are not used the pin can be used as a general purpose I O port 52 53 CS4X PA4 CS5X PA5 F Chip Select 4 output Low active Chip Select 5 output Low active PA4 or 5 When the pin is not used for the above purpose it can be used as a general purpose I O port 54 CLK PA6 F System clock output The pin outputs the same clock fre...

Page 41: ...xcept when such output is performed intentionally DACK2 Output of DMAC external transfer request acceptance ch2 This function is valid when the output of DMAC transfer request acceptance is enabled PB0 7 When each pin is not used for the corresponding purpose the pin can be used as a general purpose I O port 63 64 65 MD0 MD1 MD2 C Mode pins 0 to 2 Use these pins to set the basic MCU operation mode...

Page 42: ...SC2 UART2 clock I O Clock output can be used when UART2 clock output is enabled PE3 General purpose I O port This function is valid when UART2 clock output is disabled Table 1 5 3 Pin Functions 3 5 NO Pin name I O circuit format Function Table 1 5 4 Pin Functions 4 5 NO Pin name I O circuit format Function 75 76 DREQ0 PE4 DREQ1 PE5 F DREQ0 1 Input of DMA external transfer request This input is use...

Page 43: ...is valid when UART0 data output is enabled TRG1 External trigger input of PWM timer This function is valid when PF1 and UART0 data output is disabled PF1 General purpose I O port This function is valid when UART0 data output is disabled 81 SC0 OCPA3 PF2 F SC0 UART0 clock I O Clock output can be used when UART0 clock output is enabled OCPA3 PWM timer output This function is valid when PWM timer out...

Page 44: ...timer output This function is valid when PWM timer output is enabled PF5 General purpose I O port 85 SO2 OCPA2 PF6 F SO2 UART2 data output This function is valid when UART2 data output is enabled OCPA2 PWM timer output This function is valid when PWM timer output is enabled PF6 General purpose I O port This function is valid when UART2 data output is disabled 86 OCPA0 PF7 ATGX F OCPA0 PWM timer ou...

Page 45: ...erence voltage of A D converter high potential side Always turn the pin on or off while the voltage equal to AVRH or higher is applied to VCC 93 AVSS AVRL A D converter VSS power supply and reference voltage low potential side 94 to 96 VCC Digital circuit power supply Be sure to connect the power supply to every VCC pin 97 to 100 VSS Digital circuit ground level Table 1 5 5 Pin Functions 5 5 NO Pi...

Page 46: ...at Remarks A For 50 MHz Oscillation feedback transistor About 1 MΩ Standby control B CMOS level hysteresis input No standby control Pull up resistance About 50 kΩ C CMOS level input High voltage control enabled for flash test STANDBY X1 X0 Clock input R CMOS Diffused resistor P channel transistor N channel transistor Digital input Control signal Mode input Diffused resistor ...

Page 47: ...istor Digital input Table 1 6 2 I O circuit format 1 2 Classification Circuit format Remarks E CMOS level output Standby control F CMOS level output CMOS level hysteresis input Standby control G Analog input STANDBY Digital output Digital output Digital input Diffused resistor STANDBY Digital output Digital output Digital input Diffused resistor Digital output Digital output Diffused resistor Anal...

Page 48: ...ister 0000 0000H I O I O I O 0000 0400H I O I O I O 0000 0800H 0000 1000H 0000 1800H 0001 0000H 0001 0000H 0008 0000H 000C 0000H 000C 0800H FLASH ROM FLASH ROM 254KB 254KB 0010 0000H FFFF FFFFH FFFF FFFFH External ROM external bus mode Internal ROM external bus mode Single chip mode Direct addressing area I O map See Appendix A Access inhibited Access inhibited Access inhibited Access inhibited Ac...

Page 49: ...or I O This area is called the direct addressing area The addresses in this area can be directly specified for instruction operands The direct addressing area varies depending on the size of accessed data as follows Byte data access 0 to 0FFH Half word data access 0 to 1FFH Word data access 0 to 3FFH ...

Page 50: ...lfunction To avoid this malfunction pull it up or push it down Input of external reset signal To ensure that the device is completely reset when the L level is input to the RSTX pin the L level input to the RSTX pin must continue for at least five machine cycles Note on using an external clock When an external clock is used use the X0 pin unless otherwise specified and supply a negative phase cloc...

Page 51: ...tal oscillator or ceramic oscillator and bypass capacitor to the ground are located as near to one another as possible Also prevent the wiring of these components from crossing the wiring of other components wherever possible Such PC board artwork that places the ground around the X0 and X1 pins is strongly recommended for stable operation Treatment of NC pin Be sure to keep the NC pin open Mode p...

Page 52: ...ed only by power on reset To initialize these registers turn the power off and turn it on again to execute power on resetting Recovery from sleep or stopped state To recover from the sleep or stopped state that has been entered from a program in C bus RAM do not use an interrupt but execute resetting ...

Page 53: ...ctions including the architecture specifications and instructions 2 1 CPU Architecture 2 2 Internal Architecture 2 3 Programming Model 2 4 Data Structure 2 5 Word Alignment 2 6 Memory Map 2 7 Instruction Overview 2 8 EIT Exception Interrupt and Trap 2 9 Reset Sequence 2 10 Operation Mode ...

Page 54: ...ral purpose register x 16 Linear 4 gigabyte memory space Internal operation of the adder Addition of 32 bits x 32 bits Five cycles Addition of 16 bits x 16 bits Three cycles Enhanced interrupt processing function High speed response six cycles Support of multiple concurrent interrupts Level mask function 16 levels Enhanced I O operation instructions Inter memory transfer instruction Bit processing...

Page 55: ...e CPU The CPU is a compact implement of the 32 bit RISC FR architecture It uses a five stage instruction pipeline system to execute one instruction per cycle The pipeline consists of the following five stages Instruction fetch IF Outputs an instruction address and fetches the instruction Instruction decode ID Decodes the fetched instruction and also reads registers Execution EX Executes operation ...

Page 56: ... from the CPU the bus converter converts it into two 16 bit wide accesses to implement access to the R BUS Some internal peripheral circuits have restrictions on access width Harvard Princeton bus converter The Harvard Princeton bus converter coordinates the instruction access and data access of the CPU to implement smooth interfacing with the external bus The CPU has Harvard architecture in which...

Page 57: ... two groups General purpose registers Special registers General Purpose Registers Figure 2 3 1 shows the configuration of general purpose registers Figure 2 3 1 Configuration of general purpose registers Special Registers Figure 2 3 2 shows the configuration of special registers XXXX XXXXH XXXX XXXXH 0000 0000H 32 bits Initial value A C F P P S R 0 R 1 R 12 R 13 R 14 R 15 ...

Page 58: ... Configuration of special registers SCR CCR ILM PC PS TBR RP SSP USP MDH MDL 32 bits Program counter Program status Table base register Return pointer System stack pointer User stack pointer Multiplication division result register ...

Page 59: ...general purpose registers Figure 2 3 3 Configuration of General Purpose Registers Of 16 registers the following registers are provided for special applications with some instructions being enhanced R13 Virtual accumulator R14 Frame pointer R15 Stack pointer The initial values of R0 to R14 after resetting are undefined The initial value of R15 is 00000000H SSP value XXXX XXXXH XXXX XXXXH 0000 0000H...

Page 60: ...program being executed Bit 0 is set to 0 when the PC is updated according to instruction execution Bit 0 may be set to 1 only when an odd numbered address is specified for the branch destination address Even at this event bit 0 is invalid and an instruction must be put at an address consisting of a multiple of two The initial value after resetting is undefined XXXX XXXXH XXXX XXXXH 0000 0000H 000F...

Page 61: ...ned System stack pointer SSP SSP stands for system stack pointer When the S flag is 0 the SSP functions as R15 The SSP can be specified explicitly It can also be used as a stack pointer to specify the stack for saving the PS and PC when EIT occurs The initial value after resetting is 00000000H User stack pointer USP USP stands for user stack pointer When the S flag is 1 the USP functions as R15 Th...

Page 62: ... CPU Division When calculation begins a dividend is stored in the MDL The result of division by the DIV0S DIV0U DIV1 DIV2 DIV3 or DIV4S instruction is stored in the MDL and MDH as follows MDH Remainder MDL Quotient ...

Page 63: ...g This bit specifies the stack pointer used as R15 0 Uses SSP as R15 The bit is automatically set to 0 when EIT occurs 1 Uses USP as R15 This bit is cleared to 0 by resetting Set the bit to 0 when the RETI instruction is executed bit 4 I Interrupt enable flag This bit enables or disables a user interrupt request 0 Disables user interrupts The bit is cleared to 0 when the INT instruction is execute...

Page 64: ...tes that an overflow occurred as the result of operation The initial value after resetting is undefined bit 0 C Carry flag This bit indicates whether carry from the most significant bit or borrow occurred during operation 0 Indicates that no carry and borrow occurred 1 Indicates that carry or borrow occurred The initial value after resetting is undefined System condition code register SCR The conf...

Page 65: ...alue held by the ILM register is used for level masking Of the interrupt requests input to the CPU only those with higher interrupt levels than the level indicated by the ILM are accepted The level values range in descending order of highness from 0 00000B to 31 11111B The values that can be set from a program are limited When the original value is in the range from 16 to 31 a new value that can b...

Page 66: ... Data Mapping in Bit Ordering Mode Byte Ordering The FR series uses big endian for byte ordering Figure 2 4 2 shows data mapping in byte ordering mode Figure 2 4 2 Data Mapping in Byte Ordering Mode bit 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 MSB LSB MSB LSB bit31 23 15 7 0 10101010 11001100 11111111 00010001 bit 7 0 10101010 11001100 11111111 00010001...

Page 67: ...the FR series address alignment is performed forcibly in accordance with access width as follows Word access Addresses are aligned in multiples of four the two least significant bits are forcibly set to 00 Half word access Addresses are aligned in multiples of two on least significant bit is forcibly set to 0 Byte access As explained above some bits are forcibly set to 0 when a word or half word d...

Page 68: ...perands The size of the direct addressing area varies depending on data length Byte data 8 bits 0 to 0FFH Half word data 16 bits 0 to 1FFH Word data 32 bits 0 to 3FFH Initial vector table area The area ranging from 000FFC00H to 000FFFFFH is the EIT vector table initial area The vector table used for EIT processing can be mapped to desired addresses by rewriting the TBR The table is returned to the...

Page 69: ...The external areas cannot be accessed in single chip mode The MB91F109 assigns internal ROM area 0C0000H to 0C07FFH to 2 kilobytes of internal RAM PDR Byte I O HalfWord I O Word I O 1KB 00000000H 00000100H 00000200H 00000400H 00000800H 00000010H 00001000H 00010000H 00080000H 000C0000H 00100000H FFFFFFFFH Direct addressing area Other I O Access inhibited Internal RAM or access inhibited External ar...

Page 70: ... instructions and 32 32 bits step divide instructions are available The FR series also supports immediate transfer instructions which allow immediate data to be set in registers and inter register transfer instructions Every arithmetic operation instruction executes using the general purpose registers and multiplication division registers in the CPU Load and store Load or store instructions are us...

Page 71: ...dressing The direct addressing instructions are used for access between I O and general purpose registers or between I O and memory Specifying an I O address directly in an instruction not via a register enables high speed and highly efficient access For some instructions register indirect memory addressing with register increment decrement is also available Others Other instructions are available...

Page 72: ...on speed seems one cycle However when a valid instruction cannot be put at the delay slot the NOP instruction must be provided Example For a conditional branch instruction the instruction placed at the delay slot is executed whether the branch condition is satisfied or not For delayed branch instructions the execution order of some instructions seems to be reversed This is only applicable to PC up...

Page 73: ... the instruction in the delay slot of the CALL D instruction the data updated by the CALL D instruction is read Example LDI 32 Label R0 JMP D R0 Branches to Label LDI 8 0 R0 Does not affect the branch destination address RET D Branches to the address indicated by the RP that is set previously MOV R8 RP Does not affect the return operation ADD 1 R0 Changes the flag BC D Overflow Branches according ...

Page 74: ...is an instruction for which 1 a b c or d is indicated in the cycle count column in the list of instructions Step trace trap No step trace trap is generated between the delay slot and the execution of the branch instruction having the delay slot Interrupt NMI No interrupt NMI is accepted between the delay slot and the execution of the branch instruction having the delay slot Undefined instruction e...

Page 75: ...lot is two cycles when it involves branching or one cycle when it does not involve branching Since no dummy instruction is placed in the delay slot the instruction coding efficiency is better than that of a branch instruction with a delay slot containing a NOP instruction Selecting an operation with a delay slot when an effective instruction can be placed in the delay slot and selecting an operati...

Page 76: ... that occurs in connection with the context of the current execution Some traps such as a system call are indicated by a program Execution resumes from the instruction following the one that caused a trap EIT Characteristics Support of multiple concurrent interrupts Interrupt level mask function The user can use 15 levels Trap instruction INT EIT for emulator activation hardware and software EIT C...

Page 77: ...53 2 8 EIT Exception Interrupt and Trap Note on EIT Delay slot The delay slot of a branch instruction has restrictions on EIT See Section 2 7 Instruction Overview for details of the restrictions ...

Page 78: ...ffected by interrupt levels ILM is not changed either Table 2 8 1 Interrupt Level Level Cause Remarks Binary Decimal 00000 0 Reserved by the system When the original value of ILM is one from 16 to 31 no value within this range can be set in ILM by a program 00011 3 Reserved by the system 00100 4 INTE instruction Step trace trap 00101 5 Reserved by the system 01110 14 Reserved by the system 01111 1...

Page 79: ...instruction that sets a value from 0 to 15 is executed the specified value 16 is returned When the original value is in the range from 0 to 15 a desired value from 0 to 31 can be set Note Use the SETILM instruction to set the level to the ILM register Level Mask for Interrupt NMI When an NMI or interrupt request is issued the interrupt level see Table 2 8 1 of the interrupt cause is compared with ...

Page 80: ...evel of the corresponding interrupt cause The bits can be read and written The bits together with bit 4 enable the ICR to specify a value in the range from 16 to 31 Interrupt Control Register ICR Mapping Table 2 8 2 Assignments of interrupt causes and interrupt vectors See Chapter 8 Interrupt Controller for more information 7 6 5 4 3 2 1 0 ICR4 ICR3 ICR2 ICR1 ICR0 11111 R R W R W R W R W Initial v...

Page 81: ...rom EIT System Stack Pointer SSP The configuration of the system stack pointer SSP register is shown below Value 8 is subtracted from the stack pointer during EIT processing and 8 is added to it during returning from EIT The initial value after resetting is 00000000H The SSP also functions as general purpose register R15 when the S flag of the CCR is 0 bit31 0 00000000H Initial value SSP ...

Page 82: ...interrupt is caused the PC value is stored at the address indicated by the SSP and the PS value is stored at the address SSP 4 Interrupt Stack Figure 2 8 1 shows an example of the interrupt stack Figure 2 8 1 Example of Interrupt Stack 80000000H 7FFFFFF8H 80000000H 80000000H 7FFFFFFCH 7FFFFFFCH 7FFFFFF8H 7FFFFFF8H SSP SSP Memory Memory Before interrupt After interrupt P P S C ...

Page 83: ...he first address of the EIT vector table Table Base Register TBR The configuration of the table base register TBR is shown below The address obtained by adding the offset defined for each EIT cause to the TBR is a vector address The initial value after resetting is 000FFC00H bit31 0 000FFC00H TBR Initial value ...

Page 84: ...e per vector is 4 bytes The relationship between a vector number and vector address is represented as follows The two low order bits of the result of addition are always treated as 00 The area ranging from 000FFC00H to 000FFFFFH is the initial area of the vector table after it is reset vctadr TBR vctofs TBR 3FCH 4 x vct vctadr vector address vctofs vector offset vct vector number ...

Page 85: ...4 0A 10 Reserved by the system 3D0 0B 11 Reserved by the system 3CC 0C 12 Step trace trap 3C8 0D 13 Reserved by the system 3C4 0E 14 Undefined instruction exception 3C0 0F 15 NMI for user 3BC 10 16 Maskable interrupt cause 0 3B8 11 17 Maskable interrupt cause 1 2 300 3F 63 Maskable interrupt cause INT instruction 2FC 40 64 Reserved by the system used for REALOS 2F8 41 65 Reserved by the system use...

Page 86: ...in which an EIT event to be accepted for an EIT sequence is selected In the EIT sequence PS and PC are saved PC is updated as needed and the other EIT events are masked The handler of an EIT event accepted earlier is not always executed first Table 2 8 4 lists the priority levels for acceptance of individual EIT events After an EIT event is accepted and mask processing is performed for other event...

Page 87: ... instruction exception 3 Step trace trap 2 4 INTE instruction 2 5 NMI for user 6 INT instruction 7 User interrupt 8 Coprocessor nonexistent trap Coprocessor error trap 1 The other EIT events are discarded 2 The INTE instruction cannot be used in an environment where a step trace trap EIT event occurs Main routine NMI handler INT instruction handler Priority High NMI occurrence Low INT instruction ...

Page 88: ... defined in advance are used 2 When multiple interrupt requests have the same level the interrupt request having the smallest interrupt number is selected 3 The interrupt level of the selected interrupt request is compared with the level mask value indicated by the ILM When the interrupt level equals or exceeds the level mask value the interrupt request is masked and not accepted When the interrup...

Page 89: ... Operation for INT Instruction The operation for the INT u8 instruction is shown below The CPU branches to the interrupt handler of the vector indicated by u8 Operation SSP 4 SSP PS SSP SSP 4 SSP PC 2 SSP 0 I flag 0 S flag TBR 3FCH 4 u8 PC Operation for INTE Instruction The operation for the INTE instruction is shown below The CPU branches to the interrupt handler of the vector with vector number ...

Page 90: ...fter the T flag in the PS SCR is set to enable the step trace function user NMIs and user interrupts are inhibited No INTE EIT occurs either Operation for Undefined instruction Exception If an instruction is found undefined during instruction decoding an undefined instruction exception occurs An undefined instruction exception occurs under the following conditions The instruction is found undefine...

Page 91: ...Error Trap If an error occurs while a coprocessor is used a coprocessor error trap occurs when a coprocessor instruction that uses the coprocessor is executed afterwards No coprocessor is installed in this product Operation SSP 4 SSP PS SSP SSP 4 SSP Next instruction address SSP 0 S flag TBR 3DCH PC Operation for RETI Instruction The RETI instruction is used to return from the EIT processing routi...

Page 92: ...tialized Releasing from the external reset pin or software reset The pin is set to the predetermined state Each resource in the device is put in the reset state The control register is initialized to the predetermined value The lowest gear is selected for the clock frequency Reset Sequence After the cause of resetting is cleared the CPU executes the following reset sequence 000FFFFCH PC Note After...

Page 93: ...ed The mode pins MD2 MD1 MD0 and the BW1 and BW0 bits of the area mode registers AMD0 AMD1 AMD32 AMD4 AMD5 are used for control in this mode Mode Pins Three mode pins MD2 MD1 and MD0 are used for operation specification as shown in Table 2 10 1 Bus mode Access mode Single chip Internal ROM external bus External ROM external bus 16 bit bus width 8 bit bus width Table 2 10 1 Mode Pins and Setting Mo...

Page 94: ...o the MODR be sure to set AMD0 to AMD5 to decide the bus width of each chip select CS area The MODR has no bits used to set the bus width For a bus width the value set to mode pins MD2 to MD0 is valid before writing to the MODR and the value set to BW1 and BW0 of AMD0 to AMD5 is valid after writing to the MODR For instance external reset vectors are normally processed in the normal area 0 in which...

Page 95: ...71 2 10 Operation Mode MODR writing RSTX reset MD2 1 0 BW1 and BW0 of AMD0 to AMD5 Bus width specification ...

Page 96: ...72 CHAPTER 2 CPU ...

Page 97: ...Cycle Control Register WTCR 3 3 Standby Control Register STCR 3 4 DMA Request Suppression Register PDRR 3 5 Timebase Timer Clear Register CTBR 3 6 Gear Control Register GCR 3 7 Watchdog Timer Reset Delay Register WPR 3 8 PLL Control Register PCTR 3 9 Gear Function 3 10 Standby Mode Low Power Consumption Mechanism 3 11 Watchdog function 3 12 Reset source hold circuit 3 13 DMA suppression 3 14 Clock...

Page 98: ...pheral clock generation including the gear function Reset generation and cause retention Standby function Suppression of DMA request Built in PLL frequency multiplier circuit Registers of Clock Generator and Controller Figure 3 1 1 shows the registers of the clock generator and controller Figure 3 1 1 Clock Generator and Controller Registers 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 RSRR WTC...

Page 99: ...Selector circuit Internal clock generation circuit CPU clock Internal bus clock External bus clock Peripheral DMA clock Internal peripheral clock Stop sleep controller Internal interrupt Internal reset STCR register CPU hold permission Status transition control circuit Stop state Sleep state CPU hold request Internal reset Reset generation F F DMA suppression circuit DMA request PDRR register Rese...

Page 100: ...R When 1 the bit indicates that the reset that occurred previously was a power on reset It also indicates that the other bits of this register are invalid bit 14 Reserved This bit is reserved The value read from this bit undefined bit 13 WDOG When 1 the bit indicates that the reset that occurred previously was a watchdog reset bit 12 ERST When 1 the bit indicates that the reset that occurred previ...

Page 101: ...ed when the entire register is reset φ is twice as large as X0 when GCR CHC is 1 and is the cycle of PLL oscillation frequency when CHC is 0 Table 3 2 1 Watchdog Timer Cycles Specified by WT1 and WT0 WT1 WT0 Minimum WPR write interval required to suppress watchdog resetting Time from last 5AH write to WPR to occurrence of watchdog resetting 0 0 φ 215 Initial value φ 215 to φ 216 0 1 φ 217 φ 217 to...

Page 102: ... 1 to this bit puts the system in sleep state in which the internal CPU clock is stopped If 1 is written to both bits 7 and 6 bit 7 is given priority and therefore the system is put in a stopped state bit 05 HIZX Putting the system in a stopped state with 1 written to this bit sets the device pins at high impedance bit 04 SRST Writing 0 to this bit generates a software reset request bit 03 02 OSC1...

Page 103: ...f PLL oscillation frequency when CHC is 0 bit 01 00 Reserved These bits are reserved The value read from this bit is undefined Table 3 3 1 Oscillation Stabilization Wait Time Specified by OSC1 and OSC0 OSC1 OSC0 Oscillation stabilization wait time 0 0 φ 215 0 1 φ 217 1 0 φ 219 1 1 φ 221 Initial value ...

Page 104: ... Suppression Register PDRR The configuration of the DMA request suppression register PDRR is shown below Bit Functions of the DMA Request Suppression Register PDRR bit 11 to bit 08 D3 to D0 Writing a value other than 0 to this register suppresses any subsequent DMA transfer requests to the CPU Thereafter DMA transfer is disabled unless the register is set to 0 15 14 13 12 11 10 09 08 00000482H D3 ...

Page 105: ...Register CTBR bit 07 to bit 00 When A5H and 5AH are written successively to this register the timebase timer is cleared to 0 immediately after 5AH is written The value read from this register is undefined There is no restriction on the time interval between A5H and 5AH writing Note Clearing the timebase timer using this register temporarily changes the oscillation stabilization wait time watchdog ...

Page 106: ...ncy Source oscillation Input frequency from X0 bit 13 DBLAK This bit indicates the clock doubler operation mode Since the bit is read only a write attempt is ignored This bit is initialized by resetting Bus frequency switching involves a time lag This bit can be used to check whether operation has actually been changed This model does not support the clock doubler function 15 14 13 12 11 10 09 08 ...

Page 107: ... same gear and then set each system to a desired gear When the gear settings of both CPU and peripherals are the same before changing or the gear of only one side will be changed or when both will be set to the same gear the gear s can be set directly to the desired value DBLAK Internal external operating frequency 0 Operating at 1 1 Initial value 1 Operating at 2 1 DBLON Internal external operati...

Page 108: ...remains 0 When the system returns from the stop mode because of an external interrupt about 100 microseconds are required in addition to the oscillation stabilization wait time set in STCR OSC1 and OSC0 before PLL oscillation stabilizes Therefore do not set this bit to 0 before that See Section 3 10 1 Stop state for the procedure on returning from the stop mode and internal operation ldi 0 484 r1 ...

Page 109: ... this register is undefined There are no restrictions on the time between A5H and 5AH but the watchdog timer is reset if the writing of both data items is not finished within the time shown in Table 3 7 1 Because the flip flop is automatically cleared during the stop sleep or hold state the watchdog timer reset is delayed automatically when these conditions occur φ is twice as large as X0 when GCR...

Page 110: ... ratios The bits are initialized only at power on The internal operating frequency applicable when GCR CHC is set to 0 is written to this register bit 13 12 Reserved Always write 0 to these bits bit 11 VSTP This bit controls PLL oscillation The bit is initialized only at power on Note When the system shifts to the stop mode PLL oscillation stops regardless of the setting of this bit 15 14 13 12 11...

Page 111: ...ar controller Figure 3 9 1 Gear Controller Block Diagram Gear Function Setting The desired gear ratio for CPU clock control can be set by setting the CCK1 and CCK0 bits of the gear control register GCR to the desired values Similarly the desired gear ratio for peripheral clock control can be set by setting the PCK1 and PCK0 bits of the same register to the desired values GCR CCK PCK DBLON CHC X0 X...

Page 112: ... 0 STB R1 R2 CPU clock 1 8f Peripheral clock 1 8f f direct LDI 8 01111010b R1 CCK 01 PCK 10 CHC 0 STB R1 R2 CPU clock 1 2f Peripheral clock 1 4f f direct LDI 8 00111010b R1 CCK 00 PCK 10 CHC 0 STB R1 R2 CPU clock f Peripheral clock 1 4f f direct LDI 8 00110010b R1 CCK 00 PCK 00 CHC 0 STB R1 R2 CPU clock f Peripheral clock f f direct LDI 8 10110010b R1 CCK 10 PCK 00 CHC 0 STB R1 R2 CPU clock 1 4f P...

Page 113: ...on time based on the frequency division ratio set to bits PCK0 and PCK1 of the GCR register of the clock generator Clock generator Interrupt controller Ports D to F U TIMER channels 0 1 2 UART channels 0 1 2 A D converter 16 bit reload timer channels 0 1 2 External interrupt NMI controller Delayed interrupt module PWM timer CPU clock a CPU clock b CHC CCK value 01 00 PCK value 00 Peripheral clock ...

Page 114: ... of Sleep State In the sleep state the CPU clock and internal bus clock are stopped Power consumption when CPU operation is not required can be suppressed to a certain degree Proceed as follows to transit to the sleep state Using an instruction to write to the standby control register STCR Perform one of the following to to return to the operating state Interrupt request Issue a reset cause Since ...

Page 115: ...he pin to Hi Z Note Reset RSTX 0 SRST bit of STCR register 0 Watchdog timer reset Power on reset Mapping Addresses of Programs Used to Put Systems into Stop or Sleep State Place programs which are used to put clock systems into stop or sleep state into C bus ROM or external memory address areas Do not place them in C bus RAM ...

Page 116: ...efore writing to the STCR set the same value in CCK1 CCK0 and PCK1 PCK0 of the GCR to match the CPU clock and peripheral clock gear ratios Do not cause a transition to the stop state while the GCR CHC bit is 0 operating with PLL Before causing a transition to the stop state always set the GCR CHC bit to 1 divide by two frequency system to change the clock At least six consecutive NOP instructions ...

Page 117: ...al bus clock supply restart of internal CPU clock supply Program execution after the oscillation stabilization wait time is as follows When the level of the interrupt is enabled by the I flag of CPU ILM The program saves the register fetches the interrupt vector and executes processing beginning from the interrupt processing routine When the level of the interrupt is disabled by the I flag of CPU ...

Page 118: ...uction execution from reset entry address Notes If a peripheral interrupt request has already been issued when 1 is written to STCR register bit 7 the writing is ignored and transition to the stop state does not occur After power on resetting every internal clock is supplied to initialize the internal states However after resetting other than power on resetting no internal clock is supplied during...

Page 119: ...ng an instruction Before writing to the STCR set the same value in CCK1 CCK0 and PCK1 PCK0 of the GCR to match the CPU clock and peripheral clock gear ratios The GCR CHC bit can be any value At least six consecutive NOP instructions must be provided immediately after writing to the STCR STCR SLEP clear or Internal bus Internal interrupt Internal reset CPU hold enabled CPU hold request Sleep state ...

Page 120: ...ocessing routine When the level of the caused interrupt is disabled by the I flag of CPU ILM The program executes instructions beginning from the instruction following the instruction that caused transition to the sleep state Return by way of a reset request The procedure for returning from the stop state to the normal run state is as follows Occurrence of internal reset restart of internal bus cl...

Page 121: ... Consumption Mechanism request occur simultaneously the DMA request is given priority When transition to the sleep state has been caused by a C bus RAM program do not use an interrupt but reset instead to return from the sleep state ...

Page 122: ...tion Figure 3 10 3 Standby Mode State Transition 3 1 1 5 2 3 6 3 4 5 3 1 End of oscillation stabilization wait time 2 Cancel of reset state 3 Input of reset 4 STCR register SLEP 1 5 Input of interrupt or NMI 6 STCR register STOP 1 Power on Oscillation stabilization wait reset state Oscillation stabilization wait state Reset state Stop state Run state Sleep state ...

Page 123: ...id but subsequent settings are ignored Example Postponing Resetting Once the watchdog timer starts operation a program must regularly write A5H and 5AH to the watchdog reset postpone register WPR The watchdog reset flip flop stores the falling edge of the tap selected by the timebase timer If the flip flop has not been cleared at the second falling edge a reset signal is generated Figure 3 11 2 sh...

Page 124: ...gnored Therefore A5H must be written again Timebase Timer The timebase timer is used to supply clock pulses to the watchdog timer and is used also as the oscillation stabilization wait timer The operating clock φ is double the X0 when the GCR CHC is 1 or the cycle of the PLL oscillation frequency when the GCR CHC is 0 The value of this timebase timer is set in the RFCR and used as the count clock ...

Page 125: ...gure 3 12 1 Block Diagram of Reset Source Hold Circuit Setting for Reset Source Holding No special settings are required to use the reset source hold function Provide an instruction to read the reset source register and an instruction to branch to the appropriate program at the beginning of the program to be placed at the reset entry address PONR PONR WDOG WDOG ERST ERST SRST SRST clr SRST STCR or...

Page 126: ...r on reset checking can be placed anywhere Priorities are determined in the order of placement RESET ENTRY LDI 20 RSRR R10 LDI 8 10000000B R2 LDUB R10 R1 GET RSRR VALUE INTO R1 MOV R1 R10 R10 USED AS A TEMPORARY REGISTER AND R2 R10 WAS PONR RESET BNE PONR RESET LSR 1 R2 POINT NEXT BIT MOV R1 R10 R10 USED AS A TEMPORARY REGISTER AND R2 R10 WAS HARDWARE STANDBY RESET BNE HSTB RESET LSR 1 R2 POINT NE...

Page 127: ... Block Diagram Figure 3 13 1 is a block diagram of the DMA suppression circuit Figure 3 13 1 DMA Suppression Circuit Block Diagram Setting for DMA Suppression The DMA suppression function is used mainly in the interrupt processing routine In the interrupt processing routing the function increments the value in the DMA suppression register by one before the interrupt cause is cleared thereby preven...

Page 128: ...t is at least 15 levels higher than that of other interrupts INT ENTRY LDI 20 PDRR R10 LD R10 R1 GET PDRR VALUE INTO R1 ADD 1 R1 ST R1 R10 PDRR PDRR 1 DMA disabled LDI 20 int REG R10 int occurred with int REG LDI 8 10H R1 example int flag 10h ST R1 R10 CLEAR int REQ but still DMA disabled interrupt execute routine LDI 20 PDRR R10 LD R10 R1 GET PDRR VALUE INTO R1 ADD2 1 R1 ST R1 R10 PDRR PDRR 1 DMA...

Page 129: ...ut the timing for switching can be determined by the GCR DBLAK value When the clock doubler function is enabled the CPU clock gear becomes 1 1 regardless of the GCR setting This device permits a frequency up to double the oscillation to be set as the external bus operating frequency Therefore code as follows to enable the clock doubler function Example Disabling the Clock Doubler Function The cloc...

Page 130: ...nding on whether the Clock Doubler Function is Enabled or Disabled Table 3 14 1 lists the operating frequencies of this device that are applicable depending on the combination of settings in the GCR register and the SLCT1 and SLCT0 bits of the PCTR DOUBLER OFF LDI 20 GCR R0 BORL 0001B R0 Switches to the divide by two clock CHC 1 BANDH 1110B R0 Disables the clock doubler function DBLON 0 DOUBLER OF...

Page 131: ...tions Depending on whether the Clock Doubler Function is Enabled or Disabled GCR PLL oscillation frequency MHz Clock doubler Internal operating frequency MHz External bus frequency MHz Remarks CHC Gear Divide by two 1 1 OFF 6 25 6 25 1 2 OFF 3 12 3 12 1 4 OFF 1 56 1 56 1 8 OFF 0 78 0 78 Initial value 1 ON 6 25 3 12 PLL 3 50 0 OFF 50 0 50 0 Inhibited 1 1 25 0 OFF 25 0 25 0 1 2 25 0 OFF 12 5 12 5 1 ...

Page 132: ...g Notes The DBLON VSTP and SLCT0 bits can be set in any order No CHC 1 CHC 1 Yes No DBLON 0 DBLON 0 Yes DBLACK 0 No Yes No VSTP 0 VSTP 0 Yes WAIT 100 SLCT0 1 CHC 0 When making a PLL setting switch the clock to the divide by two clock in advance Since this model does not support the clock doubler function use the initial setting as is Restart the PLL if it is stopped Design software so that 100 mic...

Page 133: ...ler Source PLL Sample Program Load Setting Data ldi 20 GCR R0 ldi 20 PCTR R1 ldi 8 GCR_MASK R2 GCR_MASK 0000 0001 b ldi 8 PCTR_MASK R3 PCTR_MASK 0000 1000 b ldub R0 R4 read GCR register ldub R1 R5 read PCTR register st PS R15 push processor status stilm 0x0 disable interrupt and R4 R2 beq CHC_0 bra CHC_1 CHC_0 borl 0001B r0 to 1 2 clock r0 GCR register CHC DBLON CPU 12 5MHz 1 2 1 DBLACK 0 Input of...

Page 134: ...h R3 ldi 8 PCTR _MASK R3 PCTR_MASK 0000 1000 b and R5 R3 PTCR VSTP 1 beq LOOP_100US_END if VSTP 0 return bandl 0111B r1 set VSTP 0 st R2 R15 push R2 for Loop counter ldi 20 0x15E R2 wait 100 µS WAIT_100US 100us 160ns 6 25MHz 7 100 2BC cycle add2 1 R2 2BCh 2 15Eh if cache on bne WAIT_100US LOOP_100US_END ld R15 R2 Pop R2 ld R15 R3 Pop R3 ret ...

Page 135: ... Register 0 AMD0 4 6 Area Mode Register 1 AMD1 4 7 Area Mode Register 32 AMD32 4 8 Area Mode Register 4 AMD4 4 9 Area Mode Register 5 AMD5 4 10 DRAM Control Register 4 5 DMCR4 5 4 11 Refresh Control Register RFCR 4 12 External Pin Control Register 0 EPCR0 4 13 External Pin Control Register 1 EPCR1 4 14 DRAM Signal Control Register DSCR 4 15 Little Endian Register LER 4 16 Relationship between Data...

Page 136: ...megabyte areas with address and chip select pins Capable of setting a 16 bit or 8 bit bus width for each chip select area Inserting programmable automatic memory wait 7 or less cycles Support of DRAM interface 3 types of DRAM interface Double CAS DRAM usual DRAM interface Single CAS DRAM Hyper DRAM Independent control of 2 banks RAS and CAS control signals Capable of selecting 2CAS 1WE and 1CAS 2W...

Page 137: ... 15 8 7 0 Area Select Reg 1 Area Mode Reg 1 Area Select Reg 2 Area Mode Reg 2 Area Select Reg 3 Area Mode Reg 3 Area Select Reg 4 Area Mode Reg 4 Area Select Reg 5 Area Mode Reg 5 ReFresh Control Register External Pin Control 0 External Pin Control 1 DRAMControl Reg 4 DRAMControl Reg 5 ASR 1 ASR 4 ASR 3 ASR 2 ASR 5 AMR 1 AMR 5 AMR 4 AMR 3 AMR 2 AMD 0 AMD 5 AMD 1 AMD 32 AMD 4 DSCR EPCR 0 EPCR 1 DMC...

Page 138: ...AL DATA BUS MUX write buffer switch read buffer switch DATA BLOCK ADDRESS BLOCK 1or 2 EXTERNAL ADDRESS BUS inpage address buffer shifter ASR CS0X CS5X AMR comparator DRAM control RAS0 RAS1 CS0L CS1L CS0H CS1H underflow DW0X DW1X DMCR refresh counter from TBT RDX WR0X WR1X BRQ registers BGRNTX CLK control RDY ADDRESS BUS DATA BUS External pin control block Control of all blocks ...

Page 139: ...cated to a space other than the areas specified by ASR1 to ASR5 At reset time the external area other than 00010000H to 0005FFFFH becomes area 0 Figure 4 2 1 a shows an example of area 1 to area 5 located in units of 64 kilobytes from 00100000H to 0014FFFFH Figure 4 2 1 b shows an example of area 1 located in 512 kilobytes from 00000000H to 0007FFFFH and area 2 to area 5 located in 1 megabyte unit...

Page 140: ...terface to use When not specified the usual bus interface is selected DRAM interface Two channels of DRAM interface are prepared and use areas 4 and 5 3 types of DRAM interface Double CAS DRAM usual DRAM interface Single CAS DRAM Hyper DRAM High speed page mode Selection of 2CAS 1WE and 1CAS 2WE CBR refresh system Selfrefresh mode Output of RAS and CAS programmable waveforms Table 4 3 1 Correspond...

Page 141: ...us width can be optionally specified for each area by register setting A bus width set by pins MD2 MD1 and MD0 at reset time is specified for area 0 After writing to the mode register MODR a bus size is specified by the value set in the AMD0 register ...

Page 142: ...5 14 13 12 2 1 0 ASR3 Address 00000614H A31 A30 A29 A18 A17 A16 0003H W 15 14 13 12 2 1 0 ASR4 Address 00000618H A31 A30 A29 A18 A17 A16 0004H W 15 14 13 12 2 1 0 ASR5 Address 0000061CH A31 A30 A29 A18 A17 A16 0005H W Initial value Initial value Initial value Initial value Initial value Access Access Access Access Access 15 14 13 12 2 1 0 AMR1 Address 0000060EH A31 A30 A29 A18 A17 A16 0000H W 15 1...

Page 143: ...s that are set to 0 are 1 and 0 to indicate care while the ASR2 bits corresponding to the AMR2 bits that are set to 1 are 0 or 1 to indicate don t care Therefore the address space of area 2 becomes 256 kilobytes as shown below The address space of each of areas 1 to 5 can be optionally located in at least 64 kilobytes in a 4 gigabyte space using ASR1 to ASR5 and AMR1 to AMR5 When the area specifie...

Page 144: ...1 and 2 Figure 4 4 1 Sample Maps of the Chip Select Areas 00000000H 00000000H 00010000H 64KB 00020000H 00030000H 64KB 64KB 00030000H 00040000H 64KB 00040000H 0FFC0000H 64KB 00050000H 256KB 64KB 00060000H 10000000H FFFFFFFFH FFFFFFFFH Initial value Area 0 Area 0 Area 0 Values set in Examples 1 and 2 Area 2 Area 1 Area 0 Area 1 Area 2 Area 3 Area 4 Area 5 Area 0 ...

Page 145: ...wever not register values but the MD1 and MD0 pin level outputs are read at read time until writing to the MODR bit 2 to 0 WTC 2 to 0 Wait Cycle bit WTC2 to WTC0 specify the number of wait cycles to be automatically inserted when the usual bus interface is running WTC2 to WTC0 of AMD0 are reset to 111 so that seven wait cycles are automatically inserted at bus access time immediately after the res...

Page 146: ...ime After setting the mode register MODR the bus width set in AMD0 becomes valid Suppose that the width of area 0 is set to 16 bits by the MD2 MD1 and MD0 pins and wiring to the MODR is performed without setting AM0 with the bus width left as is As the initial value of BW1 and BW0 of AMD0 is 00 the bus width changes to 8 bits thereby causing an error MODR write RSTX reset CS0 bus width MD2 MD1 and...

Page 147: ...evice type does not support employing a time sharing I O bus Set this bit to 0 bit 4 and 3 BW1 and 0 Bus Width bit BW1 and BW0 specify the bus width of area 1 bit 2 to 0 WTC 2 to 0 Wait Cycle bit The WTC bits specify the number of wait cycles to be automatically inserted when the usual bus interface is operating Their operation is similar to WTC2 to WTC0 of AMD0 however they are reset to 000 and t...

Page 148: ...Bus Width bit BW1 and BW0 specify the bus width of area 2 or area 3 bit 5 to 3 WT32 to 30 Wait Cycle bit WT32 to WT30 specify the number of wait cycles to be inserted automatically when area 3 is accessed via memory The operation of the bits is similar to WTC2 to WTC0 of AMD0 The bits are reset to 000 and the number of wait cycles to be inserted becomes 0 bit 2 to 0 WT 22 to 20 Wait Cycle bit WT22...

Page 149: ...and 0 Bus Width bit BW1 and BW0 specify the bus width of area 4 These bits have functions similar to those of the BW bits of other AMD registers When the DRAM interface is used the bus width specified by these bits is also valid bit 2 to 0 WTC 2 to 0 Wait Cycle bit WTC2 to WTC0 specify the number of wait cycles to be automatically inserted when area 4 is accessed via memory These bits have functio...

Page 150: ...dth bit BW1 and BW0 specify the bus width of area 5 These bits have functions similar to those of the BW bits of other AMD registers When the DRAM interface is used the bus width specified by these bits is also valid bit 2 to 0 WTC 2 to 0 Wait Cycle bit WTC2 to WTC0 specify the number of wait cycles to be automatically inserted when area 5 is accessed via memory These bits have functions similar t...

Page 151: ...allows a page access mode a high speed page access is executed 15 14 13 12 11 10 9 8 DMCR4 Address 0000 062CH PGS3 PGS2 PGS1 PGS0 Q1W Q4W DSAS HYPR 00000000 R W 7 6 5 4 3 2 1 0 PAGE C W SLFR REFE PAR PERR PEIE 0000000 R W 15 14 13 12 11 10 9 8 DMCR5 Address 0000 062EH PGS3 PGS2 PGS1 PGS0 Q1W Q4W DSAS HYPR 00000000 R W 7 6 5 4 3 2 1 0 PAGE C W SLFR REFE PAR PERR PEIE 0000000 R W initial value initi...

Page 152: ...access bit 8 HYPR HYPeR page mode enable The HYPR bit is set to connect a DRAM with a hyper page mode to the outside 0 Double single CAS DRAM initial value 1 DRAM with hyper page mode bit 7 PAGE PAGe Enable bit The PAGE bit specifies whether to enable the high speed page mode 0 Disables high speed page mode random access operation by initial value 1 Enables high speed page mode enables high speed ...

Page 153: ...ice supports no parity function Setting this bit has no effect bit 1 PEIE Parity Error Interrupt Enable bit The PEIE bit specifies whether to output an interrupt request for a parity error This device supports no parity function Be sure to set this bit to 0 Bus Width Combinations Table 4 10 2 lists the combinations of bus widths available in areas 4 and 5 Table 4 10 2 Combinations of Bus Widths Av...

Page 154: ...hen CHC 0 For example when the PLL oscillation frequency is 25 MHz at CHC 0 one cycle equals 40 ns and 40 32 1280 ns equals one refresh interval The refresh interval is counted with the output from the timebase timer Bit Functions of Refresh Control Register RFCF bit 13 to 8 REL RELoad value bits The REL is a register to set refresh intervals At read time the count of the refresh interval downward...

Page 155: ...and the STR bit are set to 1 the CRB refresh operation is performed bit 1 and 0 CKS ClocK Select bit The CKS bits select a clock source for the downward counter The downward counter uses the divide by 32 output Φ of the timebase timer as a clock CKS1 CKS0 Source clock Maximum number of clocks 0 0 Φ initial value value 26 REL5 0 6 bits x 32 divide by 32 output 2048 0 1 Φ 8 26 REL5 0 6 bits x 32 div...

Page 156: ... control for the WR0X to WR1X pins by the WRE bit Always set this bit to 1 Even if the WRE bit is set to 1 the write pulse pin can be used as an I O port according to the bus width set by the AMD For example the WR1X pulse is not output in 8 bit mode and the corresponding pin can be used as an I O port bit 10 RDXE ReaDX pulse output Enable bit The RDXE bit specifies whether to output RDX read puls...

Page 157: ...its output initial value bit 4 COE4 Chip select Output Enable 4 The C0E4 bit controls the CS4X When this bit is reset output is permitted 0 Inhibits output 1 Permits output initial value bit 3 COE 3 Chip select Output Enable 3 The C0E3 bit controls the CS3X output When this bit is reset output is permitted In this device type because the CS3X pin also serves as the DMAC E0P1 output it is controlle...

Page 158: ... Enable 0 The C0E0 bit controls the CS0X output When this bit is reset output is permitted 0 Inhibits output 1 Permits output initial value When the external bus mode is used the C0E0 bit performs no I O port control for the CS0X pin Always set this bit to 1 ...

Page 159: ...ons of External Pin Control Register 1 EPCR1 bit 8 to 0 AE24 to AE16 Address output Enable 24 to 16 The AE24 to AE16 bits specify whether to output the corresponding addresses When the output is inhibited the register can be used as an I O port 0 Inhibits output 1 Permits output initial value AE24 to AE16 are reset to 1FFH 15 14 13 12 11 10 9 8 EPCR1 AE24 1 W Address 0000 062AH 7 6 5 4 3 2 1 0 AE2...

Page 160: ... the DW0X output When this bit is reset the output is inhibited 0 Inhibits output initial value 1 Permits output bit 5 C1HE The C1HE bit controls the CS1H output When this bit is reset the output is inhibited In this device type because the CS1H pin also serves as the DMAC DACK2 output it is controlled together with the AKSE2 and AKDE2 bits of the DMAC control register DATCR as shown below bit 4 C...

Page 161: ...it 1 RS1E The RS1E bit controls the RAS1 output When this bit is reset the output is inhibited In this device type because the RAS1 pin also serves as the DMAC E0P2 output it is controlled together with the EPSE2 and EPDE2 bits of the DMAC control register DATCR as shown below bit 0 RS0E The RS0E bit controls the RAS0 output When this bit is reset the output is inhibited 0 Inhibits output initial ...

Page 162: ...d LE0 bits are combined to specify little endian areas Note Writing to the LER register can be performed only one time after it is reset 7 6 5 4 3 2 1 0 LER Address 0000 07FEH LE2 LE1 LE0 000 W Access Initial value Table 4 15 1 Mode Setting Using the Combination of Bits LE2 LE1 and LE0 LE2 LE1 LE0 Mode 0 0 0 Initial value after reset No little endian area exists 0 0 1 Area 1 is handled as a little...

Page 163: ... data bus width and the control signals corresponding to those locations for each bus mode Data bus widths and control signals for usual bus interface Figure 4 16 1 Data bus Widths and Control Signals in Usual Bus Interface Data bus widths and control signals in DRAM interface Figure 4 16 2 Data Bus Widths and Control Signals in DRAM Interface Table 4 16 1 outlines the bus widths and control signa...

Page 164: ...FACE Table 4 16 1 Relationship between Data Bus Widths and Control Signals Bus width 16 bit bus width 8 bit bus width Data bus WR 2CAS 1WE 1CAS 2WE WR 2CAS 1WE 1CAS 2WE D31 D24 WR0X CASL WEL WR0X CAS WE D23 D16 WRIX CASH WEH ...

Page 165: ...between the internal register and external data bus for each data format Word access during execution of LD and ST instructions Figure 4 16 3 Relationship between Internal Register and External Data Bus for Word Access Half word access during execution of LDUH and STH instructions Figure 4 16 4 Relationship between Internal Register and External Data Bus for Half Word Access AA AA CC BB BB DD CC D...

Page 166: ...ernal data bus for each data bus width 16 bit bus width Figure 4 16 6 Relationship between Internal Register and External Data Bus for 16 bit Bus Width AA AA AA AA D31 D23 D15 D07 D31 D23 D31 D23 D15 D07 D31 D23 a Lower bits of output address 0 Internal register Internal register External bus External bus b Lower bits of output address 1 00 10 AA Read Write AA CC BB BB DD CC DD D31 D23 D15 D07 D31...

Page 167: ...e following items Access byte location Program address and output address Bus access count Note Because the MB91F109 detects no misalignment even if the lower 2 bits of the address specified by the program for word access are 00 01 10 or 11 the lower 2 bits of the output address are set to 00 When these bits are 00 or 01 in half word access they are set to 00 and when the bits are 10 or 11 they ar...

Page 168: ...ss First byte location of output address Data byte location for access 1 to 2 Bus access count A Word access B Half word access C Byte access Output A1 A0 10 Output A1 A0 10 Output A1 A0 10 Output A1 A0 00 Output A1 A0 00 Output A1 A0 00 Output A1 A0 00 Output A1 A0 10 a PA1 PA0 00 b PA1 PA0 01 c PA1 PA0 10 d PA1 PA0 11 a PA1 PA0 00 b PA1 PA0 01 c PA1 PA0 10 d PA1 PA0 11 Output A1 A0 00 Output A1 ...

Page 169: ...0 11 00 01 10 11 A Word access B Half word access C Byte access 1 Output A1 A0 00 2 Output A1 A0 01 3 Output A1 A0 10 4 Output A1 A0 11 1 Output A1 A0 00 2 Output A1 A0 01 3 Output A1 A0 10 4 Output A1 A0 11 1 Output A1 A0 00 2 Output A1 A0 01 3 Output A1 A0 10 4 Output A1 A0 11 1 Output A1 A0 00 2 Output A1 A0 01 3 Output A1 A0 10 4 Output A1 A0 11 PA1 PA0 00 PA1 PA0 01 PA1 PA0 10 PA1 PA0 11 a b ...

Page 170: ... between MB91F109 and External Devices MB91F109 W W D31 R D23 R 0 1 D24 X D16 X 0 1 X D15 D08D07 D00 D07 D00 16 bit device 8 bit device For the 16 8 bit device the data bus on the MSB side of the MB91F109 is used 0 1 is the lower 1 bit of the address the lower 1 bit of the address in X can be set to 0 or 1 ...

Page 171: ... access The MSB side byte data which corresponds to address 00 of big endians is the LSB side data for little endians In word access all 4 bytes in the word are binary inverted 00 11 01 10 10 01 11 00 Half word access The MSB side byte data which corresponds to address 00 of big endians is the LSB side byte data for little endians In half word access all locations of 2 bytes in a half word are exc...

Page 172: ...cess during execution of LDUB and STB instructions Figure 4 16 13 Relationship between Internal Register and External Data Bus for Byte Access BB AA AA BB D31 D07 D15 D23 D31 D23 Internal register External bus AA AA D31 D23 D15 D07 D31 D23 AA AA D31 D31 D23 D15 D07 D23 a Lower bits of output address 0 b Lower bits of output address 1 Internal register External bus Internal register External bus ...

Page 173: ...between Internal Register and External Data Bus for 16 bit Bus Width 8 bit bus width Figure 4 16 15 Relationship between Internal Register and External Data Bus for 8 bit Bus Width 00 10 AA Read Write DD BB BB CC AA CC DD D31 D23 D15 D07 D31 D23 Internal register External bus Lower part of the output address 00 01 10 11 Read Write AA DD CC BB AA BB CC DD D31 D23 D15 D07 D31 Internal register Exter...

Page 174: ...t bus width Figure 4 16 17 Example of Connection between MB91F109 and External Devices 8 Bit Bus Width MB91F109 CSnX CSmX W W D31 R D23 R 0 1 D24 X D16 X Big endian area Little endian area WR0X WR1X WR1X WR0X D31 24 D23 16 D23 16 D31 24 MSB LSB MSB LSB D15 D08D07 D00 D15 D08D07 D00 MB91F109 CSnX CSmX W W D31 R D23 R 0 1 D24 X D16 X Big endian area Little endian area D07 D00 D07 D00 ...

Page 175: ...A AA CC WR0X CASL WEL BB BB DD WR1X CASH WEH D16 CC DD D00 1 2 Internal register External pin address 0 2 D31 D31 AA DD BB WR0X CASL WEL BB CC AA WR1X CASH WEH D16 CC DD D00 1 2 Control pin Internal register External pin address 0 1 2 3 D31 D31 AA AA BB CC DD WR0X CAS WE D24 BB CC DD D00 1 2 3 4 Control pin Internal register External pin address 0 1 2 3 D31 D31 AA DD CC BB AA WR0X CAS WE D24 BB CC...

Page 176: ... CASH WEH D16 CC DD D00 1 Control pin Internal register External pin address 0 D31 D31 DD WR0XCASL WEL CC WR1XCASH WEH D16 CC DD D00 1 Control pin Internal register External pin address 0 1 D31 D31 AA BB WR0X CAS WE D24 AA BB D00 D00 1 2 Control pin Internal register External pin address 0 1 D31 D31 BB AA WR0X CAS WE D24 AA BB D00 D00 1 2 Control pin Internal register External pin address 2 3 D31 ...

Page 177: ...31 D31 BB WR1X CASH WEH D16 BB D00 1 Control pin Internal register External pin address 1 D31 D31 BB WR1X CASH WEH D16 BB D00 1 Control pin Internal register External pin address 2 D31 D31 CC WR0X CASL WEL D16 CC D00 1 Control pin Internal register External pin address 2 D31 D31 CC WR0X CASL WEL D16 CC D00 1 Control pin Internal register External pin address 3 D31 D31 DD WR1X CASH WEH D16 DD D00 1...

Page 178: ...24 BB D00 1 1 Control pin Internal register External pin address D31 D31 BB WR0X CAS WE D24 BB D00 1 1 Control pin Internal register External pin address D31 D31 CC WR0X CAS WE D24 CC D00 2 1 Control pin Internal register External pin address D31 D31 CC WR0X CAS WE D24 CC D00 2 1 Control pin Internal register External pin address D31 D31 DD WR0X CAS WE D24 DD D00 3 1 Control pin Internal register ...

Page 179: ...WE mode RAS0 Area 4 RAS Area 4 RAS Area 4 RAS Correspondence between L and H and lower 1 bit A0 of address for data bus in 16 bit mode L 0 H 1 CASL CAS corresponding to area containing 0 in A0 CASH CAS corresponding to area containing 1 in A0 WEL WE corresponding to area containing 0 in A0 WEH WE corresponding to area containing 1 in A0 RAS1 Area 5 RAS Area 5 RAS Area 5 RAS CS0L Area 4 CASL Area 4...

Page 180: ...s used one bit of the LSB area of each output address is left unconnected 8 bit data bus using 1 DRAM Figure 4 16 18 Example of Connection between MB91F109 and One 8 bit Output DRAM 8 Bit Data Bus Table 4 16 3 Page Size Select Bits PGS3 to 0 Page size Row address Column address Determine whether access is within page A31 16 A15 00 8 bit bus 16 bit bus 0000 256 A31 16 A23 08 A31 00 A31 08 A31 09 00...

Page 181: ...t DRAMs 16 Bit Data Bus This LSI COLUMN Address A08 A07 A06 A05 A04 A03 A02 A01 A00 ROW Address A16 A15 A14 A13 A12 A11 A10 A09 A08 External pin A08 A07 A06 A05 A04 A03 A02 A01 A00 A07 A06 A05 A04 A03 A02 A01 A00 RAS CASL WE RAS CAS WEL D07 00 D31 24 2 DRAMs A07 A06 A05 A04 A03 A02 A01 A00 RAS CASH WE RAS CAS WEH D07 00 D23 16 Values in parentheses are for 1CAS 2WE 8 8 ...

Page 182: ...5 Figure 4 16 20 Example of Connection between MB91F109 and Two 16 Bit Output DRAMs 16 Bit Data Bus Area4 RAS RAS0 RAS Area4 CASL CSOL UCAS Area4 CASH CS0H LCAS Area4 WE DW0X WE Area5 RAS RAS1 OE Area5CASL CS1L A8 A0 Area5CASH CS1H D16 D1 Area5 WE DW1X RAS UCAS LCAS WE RDX OE A00 not connected A09 01 A8 A0 D31 16 D16 D1 Area 4 DRAM Area 5 DRAM This LSI ...

Page 183: ...in The wait cycles take over the previous cycle and repeat the BA1 cycle until the wait request is canceled Automatic wait cycle External wait cycle DRAM Interface Chip select areas 4 and 5 can be used as DRAM spaces Set the DRME bit of AMD4 or AMD5 to control the operation by DMCR4 and DMCR5 The DRAM interface has the following three modes depending on the CAS output which are set by the DSAS and...

Page 184: ...single DRAM interface handles a CAS access as one clock cycle by setting 0 in the DSAS bit of DMCR4 and DCMR5 and 1 in the HYPR bit When using this mode set 1 in the PAGE bit of DMCR4 and DMCR5 to enable the high speed page mode The single DRAM interface starts from the Q1 to Q2 cycle as with the usual DRAM interface When the Q4 cycle is entered the CAS signal is controlled for one cycle and a rea...

Page 185: ...per DRAM interface Read Hyper DRAM interface Write Hyper DRAM interface DRAM Refresh CAS before RAS CBR refresh Automatic wait cycle of CBR refresh Selfrefresh External Bus Request Bus control release Bus control acquisition ...

Page 186: ...ddress lower 2 bits 2 of the lower 16 bits is output in the second bus cycle D31 to D16 data 31 to data 16 represent read data from external memory and I O In read cycles D31 to D16 are read at the rising edge of RDX In read cycles all data from D31 to D16 is read at the rising edge of RDX regardless of the bus width and word half word and byte access Whether the fetched data is valid is determine...

Page 187: ...are generated from decoded output addresses and remain unchanged unless those addresses change thereby changing the chip select areas set by the ASR and AMR Note that one of these signals is always asserted DACK0 to DACK2 and E0P0 to E0P2 are output in the DMA external bus cycles The DMAC register specifies whether to output these signals The output time is the same as for RDX ...

Page 188: ...ata 16 represent write data to I O In write cycles write data is output from the beginning BA1 of bus cycles and set to High Z at the end end of BA2 of bus cycles As the above example has an 8 bit data bus width write data is output from D31 to D24 In write cycles RDX is negated WR0X and WR1X are write strobe signals on the external data bus that are asserted at the falling edge of BA1 and negated...

Page 189: ...f the bus width of at least one of chip select areas 0 to 5 is set to 16 bits D23 to D16 and WR1X cannot be used as I O ports DACK0 to DACK2 and E0P0 to E0P2 are output in external bus cycles The DMAC register specifies whether to output these signals The output time is the same as WR0X to WR1X Pin D31 24 WR0X D23 16 WRIX Maximum bus width 16 bits D31 24 WR0X D23 16 WRIX 8 bits D31 24 WR0X I O por...

Page 190: ...le Timing Chart Bus width 16 bits access bytes Figure 4 17 4 Example 2 of Read Cycle Timing Chart Bus width 8 bits access words Figure 4 17 5 Example 3 of Read Cycle Timing Chart BA1 BA2 BA1 BA2 CLK A24 00 0 2 D31 24 0 2 D23 16 1 3 RDX BA1 BA2 BA1 BA2 BA1 BA2 BA1 BA CLK A24 00 0 1 2 3 D31 24 0 X 2 X D23 16 X 1 X 3 RDX X Invalid data input BA1 BA2 BA1 BA2 BA1 BA2 BA1 BA2 CLK A24 00 0 1 2 3 D31 24 0...

Page 191: ...Example 4 of Read Cycle Timing Chart Bus width 8 bits access bytes Figure 4 17 7 Example 5 of Read Cycle Timing Chart BA1 BA2 BA1 BA2 BA1 BA2 BA1 BA2 CLK A24 00 0 1 2 3 D31 24 0 1 2 3 D23 16 RDX BA1 BA2 BA1 BA2 BA1 BA2 BA1 BA CLK A24 00 0 1 2 3 D31 24 0 1 2 3 D23 16 RDX ...

Page 192: ...iming Chart Bus width 16 bits access half words Figure 4 17 9 Example 2 of Write Cycle Timing Chart Bus width 16 bits access bytes Figure 4 17 10 Example 3 of Write Cycle Timing Chart BA1 BA2 BA1 BA2 CLK A24 00 0 2 D31 24 0 2 D23 16 1 3 WR0X WR1X BA1 BA2 BA1 BA2 CLK A24 00 0 2 D31 24 0 2 D23 16 1 3 WR0X WR1X BA1 BA2 BA1 BA2 BA1 BA2 BA1 BA CLK A24 00 0 1 2 3 D31 24 0 X 2 X D23 16 X 1 X 3 WR0X WR1X ...

Page 193: ... 4 of Write Cycle Timing Chart Bus width 8 bits access bytes Figure 4 17 12 Example 5 of Write Cycle Timing Chart BA1 BA2 BA1 BA2 BA1 BA2 BA1 BA2 CLK A24 00 0 1 2 3 D31 24 0 1 2 3 D23 16 WR0X WR1X BA1 BA2 BA1 BA2 BA1 BA2 BA1 BA CLK A24 00 0 1 2 3 D31 24 0 1 2 3 D23 16 WR0X WR1X ...

Page 194: ...ip select areas When an idle cycle is inserted in between bus cycles the address of the previous bus cycle is output as is until the next bus cycle starts Because of this CS0 to CS5X which corresponds to the output address are continuously asserted The above example is a combination of 16 bit and 8 bit data buses As the maximum bus width is 16 bits D23 to D16 and WR1X do not become I O ports even ...

Page 195: ...plementing automatic wait cycles set the WTC bit of the AMD register for each chip select area The above example is an example the WTC bits are set 001 to insert one wait bus cycle in the usual bus cycles In this case it follows that 2 usual clock bus cycles 1 wait clock cycle 3 clock bus cycles Up to 7 clock cycles of automatic wait usual bus cycles 9 clock cycles can be specified BA1 BA1 BA2 BA1...

Page 196: ...rnal RDY signal set at least 1 clock of automatic wait cycle that is set 001 or more in the WTC bit of the AMD The RDY signal is detected after not during automatic wait cycles Enter the RDY signal synchronously with the falling edge of the CLK pin output If the external RDY is L at the falling edge of the CLK a wait cycle is entered and the same BA1 cycle is repeated If the external RDY is H the ...

Page 197: ...ddress specified by PGS3 to PGS0 of the DMCR as well as by the bus width The address output in the Q1 cycle is undefined D31 to D16 data 31 to data 16 represent read data from external memory and I O In read cycles D31 to D16 are fetched at the rising edge of CAS for the 1CAS 2WE and at the rising Q1 Q2 Q3 Q4 Q5 Q1 Q2 Q3 Q4 Q5 CLK 1 1CAS 2WE A24 00 X 0 row adr 0 col adr X 2 row adr 2 col adr D31 2...

Page 198: ...he PAGE bit is 0 non high speed page mode RAS becomes Normally H CAS is a column address strobe signal CASL of the 2CAS 1WE represents CAS of the upper address side 0 of the lower 1 bit and CASH represents that of the lower address side 1 of the lower 1 bit This signal is asserted at the falling edge of Q4 and negated at the falling edge of Q5 In read cycles WE including WEL and WEH is negated In ...

Page 199: ... memory and I O In write cycles write data is output from the Q1 cycle and set to High Z when the Q5 cycle ends For the 1CAS 2WE valid data is output while WEL corresponds to D31 to D24 and WEH corresponds toD23 to D16 For the 2CAS 1WE valid data is output while WE corresponds to D31 to D16 Q1 CLK X 0 row adr 0 col adr X 2 row adr 2 col adr D31 24 0 2 D23 16 1 3 RAS CAS WEL WEH RDX CS4X DACK0 EOP0...

Page 200: ...f lower 1 bit and WEH represents WE of the lower address side 1 of lower 1 bit This signal is output in write cycles asserted at the rising edge of Q4 and negated at the rising edge of the cycle next to Q5 In write cycles RDX stays at H CS4X and CS5X are output from the rising edge of the Q1 cycle DACK0 to DACK2 and E0P0 to E0P2 are output in external bus cycles Whether to output these signals is ...

Page 201: ...rts Usual DRAM Read Cycle Timing Charts Bus width 16 bits access half words Figure 4 17 18 Example 1 of Usual DRAM Read Cycle Timing Chart Q1 Q2 Q3 Q4 Q5 CLK A24 00 X 0 row adr 0 col adr D31 24 0 D23 16 1 RAS CAS WEL WEH A24 00 X 0 row adr 0 col adr D31 24 0 D23 16 1 RAS CASL CASH WE 1CAS 2WE 1 2CAS 1WE 2 ...

Page 202: ...ycle Timing Chart Q1 Q2 Q3 Q4 Q5 Q1 Q2 Q3 Q4 Q5 CLK 1 1CAS 2WE A24 00 X 0 row adr 0 col adr X 1 row adr 1 col adr D31 24 0 X D23 16 X 1 RAS CAS WEL WEH 2 2CAS 1WE A24 00 X 0 row adr 0 col adr X 1 row adr 1 col adr D31 24 0 X D23 16 X 1 RAS CASL CASH WE Upper address side Lower address side Q1 Q2 Q3 Q4 Q5 Q1 Q2 Q3 Q4 Q5 CLK A24 00 X 0 row adr 0 col adr X 1 row adr 1 col adr D31 24 0 1 D23 16 RAS CA...

Page 203: ...rts Usual DRAM Write Cycle Timing Charts Bus width 16 bits access half words Figure 4 17 21 Example 1 of Usual DRAM Write Cycle Timing Chart Q1 Q2 Q3 Q4 Q5 CLK 1CAS 2WE A24 00 X 0 row adr 0 col adr D31 24 0 D23 16 1 RAS CAS WEL WEH 2CAS 1WE A24 00 X 0 row adr 0 col adr D31 24 0 D23 16 1 RAS CASL CASH WE 1 2 ...

Page 204: ...Q1 Q2 Q3 Q4 Q5 Q1 Q2 Q3 Q4 Q5 CLK 1 1CAS 2WE A24 00 X 0 row adr 0 col adr X 1 row adr 1 col adr D31 24 0 X D23 16 X 1 RAS CAS WEL WEH 2 2CAS 1WE A24 00 X 0 row adr 0 col adr X 1 row adr 1 col adr D31 24 0 1 D23 16 X 1 RAS CASL CASH WE Upper address side Lower address side Upper address side Lower address side Q1 Q2 Q3 Q4 Q5 Q1 Q2 Q3 Q4 Q5 CLK A24 00 X 0 row adr 0 col adr X 1 row adr 1 col adr D31 ...

Page 205: ...g only one wait clock cycle to the Q1 and Q4 cycles set the Q1W and Q4W bits of DMCR4 and DMCR5 The inserted cycles are called the Q1W and Q4W cycles The Q1W and Q4W cycles execute the same cycles as the Q1 and Q4 cycles By this operation the H width of RAS and the L width of CAS can be extended by one cycle respectively Set the widths according to the DRAM access time Q1 Q1W Q2 Q3 Q4 Q4W Q5 CLK 1...

Page 206: ... L and H of WE including WEL and WEH is held Column addresses are output in Q4 and Q5 cycles Write cycle bus width 16 bits access words Figure 4 17 26 Example 2 of DRAM Interface Timing Chart in High Speed Page Mode Q1 Q2 Q3 Q4 Q5 Q4 Q5 Q4 Q5 Q4 Q5 CLK 1CAS 2WE A24 00 X 0 row adr 0 col adr 2 col adr 4 col adr 6 col adr D31 24 0 2 4 6 D23 16 1 3 5 7 RAS CAS WEL WEH RDX 1 Usual DRAM bus cycle High s...

Page 207: ...ed page mode When a bus cycle starts from a high speed page RDX in a read cycle goes down to L from the rising edge of Q4 and is negated when the Q5 cycle ends In a write cycle it goes down to L from the rising edge of WE including WEL and WEH Q4 and is negated when the Q5 cycle ends CS4X and CS5X change at the same time as the output address When a bus cycle starts from a high speed page they cha...

Page 208: ...ven if the CS area switches and another CS area is accessed RAS remains at L in high speed page mode Q4 Idle CLK A24 00 CS4X col adr CS2X basic bus CS2X basic bus CS4X col adr CS4X col adr D31 24 D23 16 CS2X CS4X RDX WR0X CS4 RAS CS4 CASL CS4 CASH CS4 WE CS4 high speed page CS2 basic bus Q5 BA1 BA2 BA1 BA2 Q4 Q5 Q4 Q5 CS4 high speed page Write Read Write Read Read Read Read Read Read Read ...

Page 209: ...e of Q4SR D31 to D16 are fetched at the rising edge of CAS including CASL and CASH as in the case of the usual DRAM interface When a read cycle ends at least one idle clock cycle is inserted so as to prevent conflicts between the external data buses DACK0 to DACK2 and E0P0 to E002 are output at the same time as CAS Q1 Q2 Q3 Q4SR Q4SR Q4SR Q4SR Q1 Q2 Q3 CLK 1 1CAS 2WE A24 00 X row adr col col col c...

Page 210: ...peration Column addresses and write data are output in Q4SW cycles CAS is asserted at the falling edge of Q4SW and negated at the rising edge or end of the Q4SW cycle WE including WEL and WEH is asserted at the rising edge of the Q4SW cycle and negated when Q4SW ends Q1 Q2 Q3 Q4SW Q4SW Q4SW Q4SW Q1 Q2 Q3 Q4SW CLK 2 2CAS 1WE A24 00 X row adr col col col col X row adr col D31 24 W W W W W D23 16 W W...

Page 211: ...hen the Q4SR cycle ends In a write cycle it goes down to L from the rising edge of WE including WEL and WEH Q4SW and is negated when the Q4SW cycle ends CS4X and CS5X change at the same time as the output address When a bus cycle starts from a high speed page they change from the Q4SR and Q4SW cycles as with the column address Q4SR BA1 BA2 Q1 Q2 Q3 Q4SW Q4SR Q4SR CLK A24 00 col CS2Xbasic bus X row...

Page 212: ...to D16 are fetched at the falling edge of CAS to be output in the Q4HR cycle next to that in which the corresponding column address is output After a read cycle ends at least one idle clock cycle is inserted so as to prevent conflicts between the external data buses DACK0 to DACK2 and E0P0 to E0P2 are output at the same time as CAS Q1 Q2 Q3 Q4HR Q4HR Q4HR Q4HR Q4HR Q1 Q3 CLK 1CAS 2WE A24 00 X row ...

Page 213: ...ing Chart Explanation of operation Column addresses and write data are output in Q4HW cycles CAS is asserted at the falling edge of Q4HW and negated at the falling edge of Q4HW WE including WEL and WEH is asserted at the rising edge of the Q4HW cycle and negated when Q4HW ends Q1 Q2 Q3 Q4HW Q4HW Q4HW Q4HW Q1 Q2 Q3 Q4HW CLK 2CAS 1WE A24 00 X row adr col col col col X row adr col D31 24 W W W W W D2...

Page 214: ...the Q4HR cycle ends In a write cycle it goes down to L from the rising edge of WE including WEL and WEH Q4HW and is negated when the Q4HW cycle ends CS4X and CS5X change at the same time as the output address When a bus cycle starts from a high speed page they change from the Q4HR and Q4HW cycles as with the column address BA1 BA2 Q1 Q2 Q3 Q4HR Q4HR Q4HW Q4HR Q4HR CLK A24 00 CS2Xbasic bus X row ad...

Page 215: ...he time describe above The priority of CRB refresh is higher than that of DRAM bus access During DRAM access for example during word access in an 8 bit bus width four times of bus access are required In this case even if a refresh request is detected from the first to third bus access the refresh is not executed until the fourth bus cycle ends CBR refresh is always executed when the last access cy...

Page 216: ...set the R3W bit of the RFCR Selfrefresh Figure 4 17 37 Example of Selfrefresh Timing Chart Explanation of operation Set the SLFR bit of DMCR4 or DMCR5 to 1 to start selfrefresh and set 0 to release it When the selfrefresh ends at least seven idle cycles are inserted In this manual selfrefresh is represented by SR1 to SR3 R1 R1W R2 R3 R3W R4 idle CLK RAS CAS wait wait SR1 SR2 SR3 SR3 SR3 idle CLK S...

Page 217: ...hen releasing bus control set the corresponding pins to High Z and assert BGRNTX one cycle later Bus Control Acquisition Figure 4 17 39 Example of Bus Control Acquisition Timing Explanation of operation When performing bus arbitration by BRQ and BGRNTX set the BRE bit of EPCR0 to 1 When acquiring bus control negate BGRNTX and activate each pin one clock later CLK A24 00 0 1 high Z D31 16 0 1 high ...

Page 218: ...n How to Choose Clocks For details on choosing the 1X and 2X clocks see Section 3 14 Clock Doubler Function A chosen clock can be optionally changed during chip operation When the clock is being switched the bus operation is temporarily suppressed When the chip is reset the 1X clock is selected automatically Figure 4 18 1 shows example of a 2X clock timing chart Figure 4 18 2 shows an example of a...

Page 219: ...18 2 Example of Timing for 1X Clock BW 16bit Access Word Read Internal clock Internal instruction Internal instruction CLK output External address bus External data bus External RDX Prefetch External fetch instruction fetch address data N N D D 2 D 2 N 4 D D 2 N 2 ...

Page 220: ...g External pin EPCR0 external RDY reception arbitration by BRQ and BGRNTX External pin DSCR DRAM pin setting Little endian LER area 2 Also observe the following notes Pins MD2 MD1 and MD0 are 001 and external vector is in 16 bit mode Before setting the mode register MODR set area 0 to the same bus width Set area 1 to area 5 such that overlapping does not occur Program Example for External Bus Oper...

Page 221: ...gister init_amd4 ldi 8 0x88 r0 DRAM 16 bit bus ldi 20 0x623 r1 amd4 register address setting stb r0 r1 Write to amd4 register init_amd5 ldi 8 0x88 r0 DRAM 16 bit bus ldi 20 0x624 r1 amd5 register address setting stb r0 r1 Write to amd5 register init_dmcr4 ldi 20 0x0c90 r0 page size 256 Q1 Q4 wait Page 1CAS 2WE CBR without parity ldi 20 0x62c r1 dmcr4 register address setting sth r0 r1 Write to dmc...

Page 222: ...er address setting ldi 20 0x61C r9 asr5 amr5 register address setting st r0 r5 Write to asr1 and amr1 registers st r1 r6 Write to asr2 and amr2 registers st r2 r7 Write to asr3 and amr3 registers st r3 r8 Write to asr4 and amr4 registers st r4 r9 Write to asr5 and amr5 registers init_ler ldi 8 0x02 r0 CS2 little endian ldi 20 0x7fe r1 ler register address setting stb r0 r1 Write to ler register in...

Page 223: ... 32 0x001a6c00 r7 CS5 address outside of the page bus_acc ld r0 r8 CS1 data word load lduh r1 r9 CS2 data half word load ld r2 r10 CS4 data word load ldub r3 r11 CS4 data byte load st r8 r4 CS4 data word store sth r9 r5 CS5 data half word store st r10 r6 CS5 data word store stb r11 r7 CS5 data byte store ...

Page 224: ...200 CHAPTER 4 BUS INTERFACE ...

Page 225: ...utlines the I O ports and explains the register configuration and the requirements for using external pins as I O pins 5 1 Outline of I O Ports 5 2 Port Data Register PDR 5 3 Data Direction Register DDR 5 4 Using External Pins as I O Ports ...

Page 226: ...Block Diagram I O Port Registers I O ports are composed of a port data register PDR and a data direction register DDR Input mode DDR 0 PDR read Reads the output level of the corresponding external pin PDR write Writes a value to the PDR Output mode DDR 1 PDR read Reads the PDR value PDR write Outputs the PDR value to the corresponding pin Data Bus 0 1 PDR read 0 pin 1 DDR PDR Resource input Resour...

Page 227: ...P54 P53 P52 P51 P50 XXXXXXXXB R W 7 6 5 4 3 2 1 0 PDR6 Address 000005H P67 P66 P65 P64 P63 P62 P61 P60 XXXXXXXXB R W 7 6 5 4 3 2 1 0 PDR7 Address 000004H P70 XB R W 7 6 5 4 3 2 1 0 PDR8 Address 00000BH P85 P84 P83 P82 P81 P80 XXXXXXB R W 7 6 5 4 3 2 1 0 PDRA Address 000009H PA6 PA5 PA4 PA3 PA2 PA1 PA0 XXXXXXXB R W 7 6 5 4 3 2 1 0 PDRB Address 000008H PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 XXXXXXXXB R W 7...

Page 228: ...dress 000606H P57 P56 P55 P54 P53 P52 P51 P50 00000000B W 7 6 5 4 3 2 1 0 DDR6 Address 000605H P67 P66 P65 P64 P63 P62 P61 P60 00000000B W 7 6 5 4 3 2 1 0 DDR7 Address 000604H P70 0B W 7 6 5 4 3 2 1 0 DDR8 Address 00060BH P85 P84 P83 P82 P81 P80 000000B W 7 6 5 4 3 2 1 0 DDRA Address 000609H PA6 PA5 PA4 PA3 PA2 PA1 PA0 0000000B W 7 6 5 4 3 2 1 0 DDRB Address 000608H PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0...

Page 229: ...Pin No Pin code Initial value Switch over register 28 to 35 P20 to P27 P20 to P27 Function automatically switches according to the mode set by MD0 to MD2 AMD0 to AMD5 and M0 to M1 Single chip P20 to P27 8 bits P20 toP27 16 bits D16 to D23 D16 to D23 36 to 42 44 P30 to P37 P30 to P37 Function automatically switches according to the mode set by MD0 to MD2 and M0 to M1 Single chip P30 to P37 External...

Page 230: ... AMD0 to AMD5 and M0 to M1 Single chip P84 and P85 8 bits WR0X and P85 16 bits WR0X and WR1X WR0X WR1X 14 to 12 PA 0 to PA2 PA 0 to PA2 EPCR0 C0E0 to C0E2 bits 0 PA0 to PA2 1 CS0X to CS2X CS0X to CS2X 11 PA3 PA3 EPCR0 C0E3 bit and DATCR EPSE1 and EPDE1 bits COE3 EPSE1 EPDE1 000 PA3 100 CS3X Others E0P1 CS3X E0P1 10 to 9 PA4 to PA5 PA4 to PA5 EPCR0 C0E4 to C0E5 bits 0 PA4 to PA5 1 CS4X to CS5X CS4X...

Page 231: ...External Bus Functions to be Selected 2 4 Pin No Pin code Initial value Switch over register Table 5 4 3 External Bus Functions to be Selected 3 4 Pin No Pin code Initial value Switch over register 92 to 91 PE2 to PE3 PE2 INT2 to PE3 INT3 SMR SCKE 0 pin values are input to SC1 and SC2 1 SC1 and SC2 output INT2 to INT3 SC1 to SC2 90 to 89 PE4 to PE5 PE4 DREQ0 to PE5 DREQ1 Pin values are always inpu...

Page 232: ...4 PF4 TRG3 SMR SOE 0 PF4 1 S01 output Pin values are always input to TRG3 during operation S01 TRG3 84 PF5 PF5 SI2 PCNL POEN 0 PF5 1 OPCA1 Pin values are always input to SI2 during operation OPCA1 SI2 85 PF6 PF6 PCNL POEN 0 PF5 1 OPCA2 SMR SOE 0 PF6 1 SO2 output OPCA2 SO2 86 PF7 PF7 PCNL POEN 0 PF6 1 OPCA2 OPCA0 72 AVCC AVCC 73 AVRH AVRH Table 5 4 3 External Bus Functions to be Selected 3 4 Pin No...

Page 233: ...rnal Pins as I O Ports Table 5 4 4 External Bus Functions to be Selected 4 4 Pin No Pin code Initial value Switch over register 74 AVSS AVRL AVSS AVRL 17 RSTX RSTX 95 X0 X0 94 X1 X1 7 16 96 46 Vcc Vcc 18 43 68 93 Vss Vss ...

Page 234: ...210 CHAPTER 5 I O PORTS ...

Page 235: ...ons of registers and operations of the external interrupt NMI controller 6 1 Overview of External Interrupt NMI Controller 6 2 Enable Interrupt Request Register ENIR 6 3 External Interrupt Request Register EIRR 6 4 External Level Register ELVR 6 5 External Interrupt Operation 6 6 External Interrupt Request Levels 6 7 Nonmaskable Interrupt NMI Operation ...

Page 236: ...ternal Interrupt NMI Controller Registers External Interrupt NMI Controller Block Diagram Figure 6 1 2 is an external interrupt NMI controller block diagram Figure 6 1 2 External Interrupt NMI Controller Block Diagram bit 7 6 5 4 3 2 1 0 EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 bit 15 14 13 12 11 10 9 8 ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 bit 7 6 5 4 3 2 1 0 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0 Enable interrupt req...

Page 237: ...ask the output of an external interrupt request The output of the interrupt requests corresponding to the register bits set to 1 is enabled EN0 enables INT0 and the requests are output to the interrupt controller The pins corresponding to the bits set to 0 retain interrupt causes but issue no request to the interrupt controller For this device writing to bits EN4 to EN7 has no effect Write 0 to th...

Page 238: ...est register EIRR is read it indicates that there are external interrupt requests When it is written the flip flops indicating these requests are cleared If a bit of the register is 1 when it is read it indicates that the corresponding pin has an external interrupt request Writing 0 to a bit of the register clears the flip flop of the interrupt request corresponding to the bit Writing 1 to the reg...

Page 239: ...T3 and defined as shown in Table 6 4 1 Suppose the level is selected for the request detection mode If input is in the active level even after each EIRR bit is cleared the corresponding bit is set again NMI is always detected at its falling edge except when it stops When it stops it is detected at the L level 7 6 5 4 3 2 1 0 ELVR Address 000099H LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0 00000000 R W Initial...

Page 240: ...e input request Selecting the L level may result in a malfunction The edge request cannot be used to return from the stop state in clock stop mode External Interrupt Operation Procedure To set the registers used for external interrupts proceed as follows 1 Disable the applicable bit of the interrupt enable register 2 Set the applicable bit of the interrupt level register 3 Clear the applicable bit...

Page 241: ...r External Interrupt Request Levels Figure 6 6 1 shows how the interrupt cause hold circuit is cleared when a level is selected for the interrupt request mode Figure 6 6 2 shows the input of an interrupt cause in interrupt enable mode and a request issued to the interrupt controller Figure 6 6 1 Clearing the Interrupt Cause Hold Circuit at Level Setting for the Interrupt Request Mode Figure 6 6 2 ...

Page 242: ...cessing is not performed after the operation restarts When NMI processing is desired after the stop state is canceled keep the NMIX pin at the L level and return it to the H level within the NMI processing routine The NMI request detection block has an NMI bit which is set by an NMI request and can be cleared only when the NMI interrupt itself is received or during a reset The NMI bit cannot be re...

Page 243: ...rview of the delayed interrupt module and explains the register configuration and functions and the operations of the delayed interrupt module 7 1 Overview of Delayed Interrupt Module 7 2 Delayed Interrupt Control Register DICR 7 3 Operation of Delayed Interrupt Module ...

Page 244: ...U Delayed Interrupt Module Register Figure 7 1 1 shows the delayed interrupt module register Figure 7 1 1 Delayed Interrupt Module Register Delayed Interrupt Module Block Diagram Figure 7 1 2 is a delayed interrupt module block diagram Figure 7 1 2 Delayed Interrupt Module Block Diagram bit7 6 5 4 3 2 1 0 Address 00000430H DLYI DICR CPU ICR IL CMP CMP DICR ICR ILM WRITE Interrupt controller Delaye...

Page 245: ... Register DICR The configuration of the delayed interrupt control register DICR is shown below Bit Function of the Delayed Interrupt Control Register DICR bit 0 DLYI This bit generates or clears an applicable interrupt cause bit7 6 5 4 3 2 1 0 DLYI 0 R W Initial value 0 Clear the cause of a delayed interrupt respectively do not issue a delayed interrupt request Initial value 1 Generate the cause o...

Page 246: ...ber A delayed interrupt is assigned to the interrupt having the largest interrupt number This model assigns the delayed interrupt to interrupt number 63 3FH DICR DLYI Bit Writing 1 to the DLYI bit of the DICR register generates the cause of a delayed interrupt Writing 0 clears the cause of the delayed interrupt This bit is the same as the interrupt source flag for general interrupts Clear the bit ...

Page 247: ...pter also explains the hold request cancel request function using examples 8 1 Overview of Interrupt Controller 8 2 Interrupt Controller Block Diagram 8 3 Interrupt Control Register ICR 8 4 Hold Request Cancel Request Level Setting Register HRCL 8 5 Priority Check 8 6 Returning from Standby Mode Stop Sleep 8 7 Hold Request Cancel Request 8 8 Example of Using the Hold Request Cancel Request Functio...

Page 248: ...Hold request cancel request generator Major Interrupt Controller Functions The major functions of the interrupt controller are as follows Detection of NMI interrupt requests Priority check based on the level or number Transmission of the interrupt level of the cause selected as the result of checking to the CPU Transmission of the interrupt number of the cause selected as the result of checking to...

Page 249: ...1 ICR0 Address 0000040EH ICR4 ICR3 ICR2 ICR1 ICR0 Address 0000040FH ICR4 ICR3 ICR2 ICR1 ICR0 Address 00000410H ICR4 ICR3 ICR2 ICR1 ICR0 Address 00000411H ICR4 ICR3 ICR2 ICR1 ICR0 Address 00000412H ICR4 ICR3 ICR2 ICR1 ICR0 Address 00000413H ICR4 ICR3 ICR2 ICR1 ICR0 Address 00000414H ICR4 ICR3 ICR2 ICR1 ICR0 Address 00000415H ICR4 ICR3 ICR2 ICR1 ICR0 Address 00000416H ICR4 ICR3 ICR2 ICR1 ICR0 Addres...

Page 250: ...ess 00000425H Address 00000426H Address 00000427H Address 00000428H Address 00000429H Address 0000042AH Address 0000042BH Address 0000042CH Address 0000042DH Address 0000042EH Address 0000042FH ICR4 ICR3 ICR2 ICR1 ICR0 R R W R W R W R W Address 00000431H LVL4 LVL3 LVL2 LVL1 LVL0 R R W R W R W R W ICR32 ICR33 ICR34 ICR35 ICR36 ICR37 ICR38 ICR39 ICR40 ICR41 ICR42 ICR43 ICR44 ICR45 ICR46 ICR47 HRCL ...

Page 251: ...5 NMI LEVEL4 to 0 4 HLDCAN ICR00 RI00 6 VCT5 to 0 ICR47 RI47 DLYIRQ DLYI 1 2 3 R BUS NMI processing VECTOR check LEVEL and VECTOR generation HLDREQ cancel request 1 DLYI is the delayed interrupt module See Chapter 7 Delayed Interrupt Module for more information 2 INT0 is a wakeup signal for the clock controller in sleep or stop state 3 HLDCAN is a bus yield request signal to a bus master other tha...

Page 252: ...ntrol Register ICR bit 4 to 0 ICR 4 to 0 These are the interrupt level setting bits that are used to specify the interrupt level of the corresponding interrupt request When the interrupt level specified by this register equals or exceeds the level mask value set in the CPU ILM register the CPU masks the interrupt request When the register is reset the bits are initialized to 11111B Table 8 3 1 sum...

Page 253: ...ls ICR4 ICR3 ICR2 ICR1 ICR0 Interrupt level 0 0 0 0 0 0 System reserved 0 1 1 1 0 14 0 1 1 1 1 15 NMI 1 0 0 0 0 16 Highest level that can be set 1 0 0 0 1 17 High Low 1 0 0 1 0 18 1 0 0 1 1 19 1 0 1 0 0 20 1 0 1 0 1 21 1 0 1 1 0 22 1 0 1 1 1 23 1 1 0 0 0 24 1 1 0 0 1 25 1 1 0 1 0 26 1 1 0 1 1 27 1 1 1 0 0 28 1 1 1 0 1 29 1 1 1 1 0 30 1 1 1 1 1 31 Interrupt prohibited ...

Page 254: ...ng register HRCL is as follows Bit Functions of Hold Request Cancel Request Level Setting Register HRCL bit4 to 0 LVL4 to 0 These bits specify the interrupt level for issuing a hold request cancel request to the bus master When an interrupt request having a level higher than the interrupt level set in this register is generated a hold request cancel request is issued to the bus master The LVL4 bit...

Page 255: ...ong interrupt causes numbers and levels Table 8 5 1 Relationships among Interrupt Causes Numbers and Levels 1 2 Cause of interrupt Interrupt number Interrupt level Offset TBR default address Decimal Hexadecimal NMI request 15 0F 15 FH fixed 3C0H 000FFFC0H External interrupt 0 16 10 ICR00 3BCH 000FFFBCH External interrupt 1 17 11 ICR01 3B8H 000FFFB8H External interrupt 2 18 12 ICR02 3B4H 000FFFB4H ...

Page 256: ...nterrupt Causes Numbers and Levels 1 2 Cause of interrupt Interrupt number Interrupt level Offset TBR default address Decimal Hexadecimal Table 8 5 2 Relationships among Interrupt Causes Numbers and Levels 2 2 Cause of interrupt Interrupt number Interrupt level Offset TBR default address Decimal Hexadecimal U TIMER 0 42 2A ICR26 354H 000FFF54H U TIMER 1 43 2B ICR27 350H 000FFF50H U TIMER 2 44 2C I...

Page 257: ... instruction used in an interrupt routine See Section 2 8 EIT Exception Interrupt and Trap for details Reserved by the system 54 36 324H 000FFF24H Reserved by the system 55 37 320H 000FFF20H Reserved by the system 56 38 31CH 000FFF1CH Reserved by the system 57 39 318H 000FFF18H Reserved by the system 58 3A 314H 000FFF14H Reserved by the system 59 3B 310H 000FFF10H Reserved by the system 60 3C 30CH...

Page 258: ...ult The same operations are performed for returning from the sleep state In the sleep state the register in this module can be accessed using DMAC Notes An NMI request also causes a return from the stop state For an interrupt cause that should not trigger a return from the stop or sleep state use the corresponding peripheral control register to inhibit the output of the interrupt request Since the...

Page 259: ...L register range from 10000B to 11111B as with the ICR register When 11111B is set a cancel request is issued for every interrupt level When 10000B is set a cancel request is issued only for NMI Table 8 7 1 lists the settings for the interrupt levels for which a hold request cancel request is issued After the HRCL register is reset hold requests for all interrupt levels are canceled In this situat...

Page 260: ...s module Set a level higher than that set in the HRCL register in the ICR corresponding to the interrupt cause used Postpone DMA request register PDRR Clock controller The PDRR is used to temporarily suppress a hold request from DMA and prevent the CPU from returning to the hold state when the interrupt cause is cleared A hold request from DMA is transmitted to the CPU only when the value of this ...

Page 261: ...nging the interrupt level and rendering HRCR inactive Accordingly HRCR is inactivated to allow DMA to issue a hold request but the hold request is interrupted because PDRR is not 0 The hold request is transmitted to the CPU to allow DMA transfer again only after PDRR is decremented 3 Example of multiple interrupt routine Figure 8 8 3 Example of Timing for Hold Request Cancel Request Sequence Inter...

Page 262: ... PDRR at the beginning of the interrupt routine to be executed during DMA transfer in CPU hold state and decrement it at the exit of the routine to prevent DMA transfer during execution of the interrupt routine On the other hand incrementing or decrementing PDRR during execution of an ordinary interrupt routine prevents DMA transfer during execution of the interrupt routine and may deteriorate per...

Page 263: ...9 U TIMER This chapter provides an overview of the U TIMER and explains the register configuration and functions and the operations of the U TIMER 9 1 Overview of U TIMER 9 2 U TIMER Registers 9 3 U TIMER Operation ...

Page 264: ...ins three channels of U TIMER When the U TIMER is used as an interval timer two channels 0 and 1 of U TIMER can be cascaded to count up to 232 φ φ φ φ interval U TIMER Registers Figure 9 1 1 shows the U TIMER registers Figure 9 1 1 U TIMER Registers U TIMER Block Diagram Figure 9 1 2 is a U TIMER block diagram Figure 9 1 2 U TIMER Block Diagram 15 8 7 0 UTIM R UTIMR W UTIMC R W 15 0 UTIMR reload r...

Page 265: ...s the U TIMER operation bit 7 UCC1 U timer Count Control 1 The UCC1 bit controls the U TIMER counting method n Value set in UTIMR α Cycle of clock output to UART 15 14 2 1 0 UTIM ch0 Address 0000 0078H b15 b14 b2 b1 b0 ch1 Address 0000 007CH ch2 Address 0000 0080H R 0 Access initial value 15 14 2 1 0 UTIMR ch0 Address 0000 0078H b15 b14 b2 b1 b0 ch1 Address 0000 007CH ch2 Address 0000 0080H W 0 in...

Page 266: ...clock source Initial value 1 Use the underflow signal of channel 1 for the source clock timing of U TIMER channel 0 f f in the block diagram CLKS is valid only for channel 0 Always set CLKS to 0 for channel 1 bit 1 UTST U TIMER STart UTST is the operation enable bit for the U TIMER 0 Stop Writing 0 to this bit stops the U TIMER even during operation Initial value 1 Run Writing 1 to this bit during...

Page 267: ...mode Cascade Mode U TIMER channels 0 and 1 can be used in cascade mode Figure 9 3 1 shows an example of cascade mode in which UTIMR channel 0 is set to 0100 and UTIMR channel 1 is set to 0002 Figure 9 3 1 Example of Using U TIMER Channels 0 and 1 in Cascade Mode n UTIMR Reload value bps UCC1 0 2n 2 16 Peripheral machine clock frequency variable with the gear bps UCC1 1 2n 3 16 n UTIMR Reload value...

Page 268: ...244 CHAPTER 9 U TIMER ...

Page 269: ...R 10 3 Serial Control Register SCR 10 4 Serial Input Data Register SIDR and Serial Output Data Register SODR 10 5 Serial Status Register SSR 10 6 UART Operation 10 7 Asynchronous Start Stop Mode 10 8 CLK Synchronous Mode 10 9 UART Interrupt Occurrence and Flag Setting Timing 10 10 Notes on Using the UART and Example for Using the UART 10 11 Setting Examples of Baud Rates and U TIMER Reload Values ...

Page 270: ...tion Support for setting any baud rate using external clocks Error detection function parity errors framing errors and overrun NRZ code for transfer signal Support for starting DMA transfer by an interrupt UART Registers Figure 10 1 1 shows the UART registers Figure 10 1 1 UART Registers 15 8 7 0 SCR SMR R W SSR SIDR R SODR W R W 8 bit 8 bit 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 SIDR SODR 7 6 5 ...

Page 271: ...n circuit Reception clock Transmission clock SC clock Transmision interrupt to CPU received data Reception control circuit Start bit detection circuit Reception bit counter Reception parity counter Transmission control circuit Tranmission start circuit Tranmission bit counter Tranmission parity counter Transmit data Reception status check circuit Reception shifter End of reception Transmission shi...

Page 272: ...PU This resource cannot recognize the format of received data and thus supports only the master in multiprocessor mode Since the parity check function cannot be used set PEN of the SCR register to 0 bit 5 4 reserved Always set these bits to 1 bit 3 CS0 Clock Select This bit selects the UART operating clock 0 Built in timer U TIMER Initial value 1 External clock bit 2 reserved Always set this bit t...

Page 273: ... clock mode 0 Clock input pin initial value 1 Clock output pin Note To use the SC pin as a clock input pin set the CS0 bit in advance to 1 to select the external clock bit 0 SOE Serial Output Enable There is an external pin SO that is also designed to be used for a general purpose I O port pin This bit specifies whether to use the external pin SO as a serial output pin or an I O port pin 0 General...

Page 274: ...s start stop communication No parity bit can be added in multiprocessor mode mode 1 or CLK synchronous communication mode mode 2 bit 6 P Parity This bit specifies whether to use even or odd parity when a parity bit is added for data communication 0 Even parity Initial value 1 Odd parity bit 5 SBL Stop Bit Length This bit specifies the number of stop bits used as a frame end mark in asynchronous st...

Page 275: ... is always 1 bit 1 RXE Receiver Enable This bit controls UART receive operation 0 Disable UART receive operation Initial value 1 Enable UART receive operation Note If the UART receive operation is disabled during reception processing while data is input to the reception shift register the receive operation is stopped when the reception of the current frame is completed and the received data is sto...

Page 276: ...Configuration of Serial Input Data Register SIDR and Serial Output Data Register SODR The configuration of the serial input data register SIDR and serial output data register SODR is shown below Note An instruction to write to the above address means to write to the SODR register and an instruction to read from the above address means to read the SIDR register 7 6 5 4 3 2 1 0 SIDR 00001DH Address ...

Page 277: ... Initial value 1 A parity error is present bit 6 ORE Over Run Error This bit is an interrupt request flag that is set when an overrun is detected for received data To clear the flag once it is set set the REC bit of the SCR register to 0 When this bit is set SIDR data is invalidated 0 No overrun is present Initial value 1 An overrun is present bit 5 FRE FRaming Error This bit is an interrupt reque...

Page 278: ...he SODR register When the written data is loaded to the transmission shifter and transmission begins the bit is set again to indicate that the next instance of transmission data can be written 0 Transmission data cannot be written 1 Transmission data can be written Initial value bit 2 reserved bit 1 RIE Receiver Interrupt Enable This bit controls receiver interrupts 0 Disable interrupts Initial va...

Page 279: ...isted below UART Clock Selection Internal timer When the U TIMER is selected while CS0 is set to 0 the baud rate is determined by the reload value set for the U TIMER The baud rate is calculated as follows Asynchronous start stop φ 16 β CLK synchronous φ β φ Peripheral machine clock frequency β Cycle set by the U TIMER 2n 2 or 2n 3 where n is a reload value The baud rate for transmission in asynch...

Page 280: ...ART External clock When the external clock is selected with 1 set in CS0 the baud rate is determined as follows f is the external clock frequency Asynchronous start stop f 16 CLK synchronous f f can be up to 3 125 MHz ...

Page 281: ...has been received an error flag is set and the RDRF flag bit 4 of the SSR register is set subsequently thereby causing a receiver interrupt to the CPU if the RIE bit bit 1 of the same SSR register has been set to 1 Ensure in the program design that the flags of the SSR register are checked and the SIDR register is read if normal reception is indicated while the necessary processing for a counterme...

Page 282: ...e must be supplied after ensuring that there is data in the transmission data buffer SODR register of the UART on the transmitting end The TDRE flag is 0 The mark level before and after transmission must also be ensured The data length can only be eight bits and no parity bit can be added Since no start and stop bits are used only overrun errors are detected Initialization The values that must be ...

Page 283: ...ing no interrupt TIE 0 Start of communication Writing to the SODR register starts communication Dummy transmission data must be written to the SODR register even for reception only End of communication The end of communication can be detected by the fact that the RDRF flag of the SSR register changes to 1 Check the ORE bit of the SSR register to determine whether communication has been successful ...

Page 284: ...m the SIDR register Mode 1 does not support the parity check function and mode 2 does not support the parity check and framing error detection functions TDRE is set when the SODR register is emptied and ready to accept the next instance of write data and is cleared when the next data item is written to the SODR register In data receptuion mode PE ORE FRE or RDRF is used to request an interrupt In ...

Page 285: ...st bit bit 9 indicates an address or that data is invalid If ORE or FRE is active the SIDR data is invalid Figure 10 9 2 ORE FRE and RDRF Set Timing Mode 1 Interrupt Flag Set Timing for Data Reception in Mode 2 When the last data item D7 is detected after data reception transfer is completed the ORE and RDRF flags are set to issue an interrupt request to the CPU If ORE is active the SIDR data is i...

Page 286: ...ing the transmission shifter and inhibiting UART transmit operation When a 0 is written to TXE or RXE in mode 2 of the SCR register during transmission data written to the SODR register before transmission is stopped is transmitted Figure 10 9 4 TDRE Set Timing Mode 0 or 1 Figure 10 9 5 TDRE Set Timing Mode 2 TDRE ST D0 D1 D2 D3 D4 D5 D6 D7 SP SP ST D0 D1 D2 D3 A D SO interrupt SO output ST Starte...

Page 287: ...R after data transfer or immediately after transmission begins Example for Use of the UART In mode 1 multiple slave CPUs are connected to one host CPU as shown in Figure 10 10 1 This resource supports only the communication interface on the host end Figure 10 10 1 Sample System Structure for Mode 1 Communication begins with address data transfer by the host CPU Address data is indicated by the fac...

Page 288: ...RT Host CPU Set 0 in A D Communication with slave CPU Set transfer mode to 1 Set address data in D0 to D7 to select the slave CPU and set A D to 1 then transfer one byte Enable the receive operation Is the communication finished Communicate with another slave CPU Disable the receive operation ...

Page 289: ...11 1 Baud Rates and U TIMER Reload Values in Asynchronous Start Stop Mode Baud rate µ µ µ µs 25 MHz 20 MHz 12 5 MHz 10 MHz 1200 833 33 650 UCC1 0 520 UCC1 0 324 UCC1 1 259 UCC1 1 2400 416 67 324 UCC1 1 259 UCC1 1 162 UCC1 0 129 UCC1 0 4800 208 33 162 UCC1 0 129 UCC1 0 80 UCC1 1 64 UCC1 0 9600 104 17 80 UCC1 1 64 UCC1 0 39 UCC1 1 31 UCC1 1 19200 52 08 39 UCC1 1 31 UCC1 1 19 UCC1 1 38400 26 04 19 UC...

Page 290: ...266 CHAPTER 10 UART ...

Page 291: ...d explains the register configuration and functions and the operations of the A D converter 11 1 Overview of A D Converter Successive Approximation Type 11 2 Control Status Register ADCS 11 3 Data Register ADCR 11 4 A D Converter Operation 11 5 Conversion Data Protection Function 11 6 Notes on Using the A D Converter ...

Page 292: ...rogrammed Continuous conversion mode The specified channel is converted repeatedly Convert and stop mode When one channel is converted the converter stops and waits for the next activation the beginning of conversion can be synchronized DMA transfer activated by an interrupt Choices of software external trigger falling edge and reload timer rising edge for activation A D Converter Registers Figure...

Page 293: ... Diagram of the A D Converter AVCC AVR AVSS MPX AN0 AN1 AN2 AN3 ADCR ADCS ATGX R B U S Input circuit Internal voltage generator Sample hold circuit Comparator Successive approximation register Decoder Data register Trigger activation A D control register TIMO internal connection Reload timer channel 2 Timer activation Operating clock Peripheral clock Prescaler ...

Page 294: ...operation cannot be set to 1 An RMW instruction reads 1 from the bit In single mode the bit is cleared when A D conversion is finished In continuous conversion or convert and stop mode the bit is not cleared until it is set to 0 to forcibly terminate A D conversion The bit is initialized to 0 when the register is reset Do not perform forced termination and software activation simultaneously BUSY 0...

Page 295: ...ring the following converted data items until the current data in the data register is transferred by DMA A D conversion is stopped during this period A D conversion resumes after DMA transfer is finished This bit is effective only when DMA is used See Section 11 5 Conversion Data Protection Function for more information The bit is cleared when the register is reset bit 11 10 STS1 STS0 STart Sourc...

Page 296: ...in write mode bit 7 6 MD1 MD0 A D converter MoDe set Select the operating mode These bits are initialized to 00 by a reset Table 11 2 2 Selecting the A D Converter Operation Mode MD1 MD0 Operation mode 0 0 Single conversion mode in which restart in any mode is enabled during operation 0 1 Single conversion mode in which no restart is enabled during operation 1 0 Continuous conversion mode in which...

Page 297: ...these bits When read these bits indicates the channel over which A D conversion is being performed When read while the A D converter is stopped in convert and stop mode the bits indicate the channel over which A D conversion has been previously completed These bits are initialized to 000 when the register is reset bit2 1 0 ANE2 ANE1 ANE0 ANalog End channel set These bits are used to set the A D co...

Page 298: ...channel set by these bits in continuous conversion or convert and stop mode the A D converter returns to the start channel set by ANS2 to ANS0 When setting the channels observe the rule that ANE equals or exceeds ANS Example ANS sets channel 1 and ANE sets channel 3 in single conversion mode A D conversion is performed from channel 1 to channel 2 and then channel 3 These bits are initialized to 00...

Page 299: ...ion is completed Normally the value converted last is stored The value of this register is undefined when the register is reset Reading the high order bits 10 to 15 results in 0 The conversion data protection function is supported See Section 11 5 Conversion Data Protection Function for this function bit 15 14 13 12 11 10 9 8 ADCR Address 000038H 0 0 0 0 0 0 X X R R R R R R R R bit 7 6 5 4 3 2 1 0...

Page 300: ...hannel is converted Single conversion mode In single mode analog input set by the ANS bit and ANE bit of ADCS is converted in order When the conversion of the end channel set by the ANE bit is completed the A D converter stops its operation If the start channel and the end channel are the same ANS ANE one channel conversion is adopted Example ANS 000 ANE 011 Start AN0 AN1 AN2 AN3 End ANS 010 ANE 0...

Page 301: ...er conversion of the analog input from one channel is completed The converter restarts conversion at the next start cause When conversion is completed up to the end channel specified by the ANE bits the converter returns to the ANS analog input and continues A D conversion If the start and end channels are the same ANS ANE conversion of the analog input from only one channel is repeated Example AN...

Page 302: ...s data has already been transferred when current conversion is finished the A D converter continues conversion without stopping Notes The conversion data protection function is affected by the ADCS INT and INTE bits The function works only when interrupts are enabled INTE 1 The function does not work when interrupts are disabled INTE 0 and conversion data overwrites the register successively and p...

Page 303: ...tart of continuous A D conversion End of one cycle of conversion Store conversion data in data register End of 2nd cycle of conversion Start DMAC End of transfer Stop A D converter temporarily Store conversion data in data register End of third conversion Start DMAC Continue End of last conversion Start DMAC and transfer Stop A D converter 1 Restarting the A D converter in stopped state may lead t...

Page 304: ...ger or the internal timer is used to start the A D converter In this case set the external trigger or internal timer input value at the inactive side Setting it on the active side causes malfunction When setting STS1 and STS0 set the ATGX and reload timer as follows ATGX 1 input and reload timer channel 2 0 output Other Notes on Using the A D Converter If the external impedance is higher than the ...

Page 305: ...mer and explains the register configuration and functions and operations of the 16 bit reload timer 12 1 Overview of 16 Bit Reload Timer 12 2 Control Status Register TMCSR 12 3 16 Bit Timer Register TMR and 16 bit Reload Register TMRLR 12 4 Operation of 16 Bit Reload Timer 12 5 Counter States ...

Page 306: ...start DMA transfer The MB91F109 contains three channels of 16 bit reload timer The channel 2 T0 output of the reload timer is connected to the A D converter inside the LSI chip Therefore A D conversion can be started periodically as specified in the reload register 16 Bit Reload Timer Registers Figure 12 1 1 shows the 16 bit reload timer registers Figure 12 1 1 16 Bit Reload Timer Registers 15 14 ...

Page 307: ... diagram Figure 12 1 2 16 Bit Reload Timer Block Diagram 16 8 RELD UF OUTE 16 OUTL 2 OUT INTE GATE CTL 2 UF IRQ CSL1 CNTE CSL0 TRG 2 IN CTL EXCK PWM ch 0 ch 1 3 A D ch 2 21 23 25 MOD2 MOD1 MOD0 3 R B U S 16 bit reload register Reload Clock selector Retrigger Prescaler clearing Internal clock 16 bit decrementing counter ...

Page 308: ... bits specify the operation mode Always set these bits to 0 bit 6 OUTE OUTput Enable Always set this bit to 0 bit 5 OUTL Always set this bit to 0 bit 4 RELD This is a reload enable bit Setting this bit to 1 enables the reload mode When the counter value underflows from 0000H to FFFFH in reload mode the value in the reload register is loaded to the counter and the counter continues counting When th...

Page 309: ...e bit to 1 has no effect A Read Modify Write instruction reads 1 from this bit bit 1 CNTE This is a timer count enable bit Setting this bit to 1 makes the timer wait for a start trigger signal Setting the bit to 0 stops the counter bit 0 TRG This is a software trigger bit Setting the bit to 1 activates the software trigger which loads the value in the reload register to the counter to start counti...

Page 310: ...er is used to read the count value of the 16 bit timer The initial value is undefined Always use a 16 bit data transfer instruction to read the register 16 Bit Reload Register TMRLR The 16 bit reload register TMRLR holds the initial count value The initial value is undefined Always use a 16 bit data transfer instruction to write to this register 15 0 TMR 00002AH 000032H 00003EH R R R R R R R R R A...

Page 311: ...tart and operation timing chart Time T peripheral clock machine cycle is required from when a counter start trigger is input to when the reload register data is loaded to the counter Figure 12 4 1 Counter Start and Operation Timing Underflow Operation An underflow occurs when the counter value changes from 0000H to FFFFH That is an underflow occurs at a count of reload register value 1 If the RELD...

Page 312: ...CHAPTER 12 16 BIT RELOAD TIMER Figure 12 4 2 Underflow Operation Timing 0000H RELD 1 0000H FFFFH RELD 0 1 1 1 Count clock Counter Data loading Underflow setting Underflow set Counter Count clock Reload data ...

Page 313: ...12 5 1 Counter States Transition CNTE 0 WAIT 1 CNTE 0 CNTE 0 CNTE 1 CNTE 1 TRG 0 TRG 1 CNTE 1 WAIT 1 CNTE 1 WAIT 0 RELD TRG 1 TRG 1 RELD UF CNTE 1 WAIT 0 STOP RESET WAIT UF LOAD RUN State transition by hardware State transition by register access Counter Operates The contents of the reload register are loaded to the counter Loading is completed Counter Holds the value at a stop Immediately after r...

Page 314: ...290 CHAPTER 12 16 BIT RELOAD TIMER ...

Page 315: ...the bit search module It explains the register configuration functions operations and the save restore processing of the bit search module 13 1 Overview of the Bit Search Module 13 2 Bit Search Module Registers 13 3 Bit Search Module Operation and Save Restore Processing ...

Page 316: ...e 13 1 1 Bit Search Module Registers Block Diagram of Bit Search Module Figure 13 1 2 is a block diagram of the bit search module Figure 13 1 2 Block Diagram of the Bit Search Module 31 0 Address 000003F0H Address 000003F4H Address 000003F8H Address 000003FCH BSD0 BSD1 BSDC BSRR 0 detection data register 1 detection data register Detection result register Change point detection data register D BUS...

Page 317: ...to this register The initial value after resetting is undefined The value read from this register is undefined Use a 32 bit data transfer instruction for data transfer do not use 8 bit and 16 bit data transfer instructions 1 Detection Data Register BSD1 Use a 32 bit data transfer instruction for data transfer do not use 8 bit and 16 bit data transfer instructions Write The module detects 1 for the...

Page 318: ...d Change Point Detection Data Register BSDC The module detects a change point for the value written to this register The initial value after resetting is undefined The value read from this register is undefined Use a 32 bit data transfer instruction for data transfer do not use 8 bit and 16 bit data transfer instructions Detection Result Register BSRR The result of 0 detection 1 detection or chang...

Page 319: ...ata Read value decimal 11111111 11111111 11110000 00000000B FFFFF000H 20 11111000 01001001 11100000 10101010B F849E0AAH 5 10000000 00000010 10101010 10101010B 8002AAAAH 1 11111111 11111111 11111111 11111111B FFFFFFFFH 32 1 Detection The module scans the data written to the 1 detection data register from MSB to LSB and returns the position where the first 1 is detected The detection result can be o...

Page 320: ...00100000 00000000 00000000 00000000B 20000000H 2 00000001 00100011 01000101 01100111B 01234567H 7 00000000 00000011 11111111 11111111B 0003FFFFH 14 00000000 00000000 00000000 00000001B 00000001H 31 00000000 00000000 00000000 00000000B 00000000H 32 11111111 11111111 11110000 00000000B FFFFF000H 20 11111000 01001001 11100000 10101010B F849E0AAH 5 10000000 00000010 10101010 10101010B 8002AAAAH 1 1111...

Page 321: ...data register and store the read data Save 2 Use the bit search module 3 Write the data saved in step 1 to the 1 detection data register Restore As a result of the above operation the value obtained by reading the next detection result register corresponds to the data written to the bit search module before step 1 Even if the last register to which data was written is a 0 detection or point change...

Page 322: ...298 CHAPTER 13 BIT SEARCH MODULE ...

Page 323: ...WM Timer Block Diagram 14 3 Control Status Register PCNH PCNL 14 4 PWM Cycle Setting Register PCSR 14 5 PWM Duty Cycle Setting Register PDUT 14 6 PWM Timer Register PTMR 14 7 General Control Register 1 GCN1 14 8 General Control Register 2 GCN2 14 9 PWM Operation 14 10 One shot Operation 14 11 Interrupts 14 12 Constant L or Constant H Output from PWM Timer 14 13 Starting Multiple PWM Timer Channels...

Page 324: ...Data register for reloading containing a buffer Duty cycle setting register Compare register containing a buffer Transfer from the buffer is triggered by a counter borrow Pin control The pin is set to 1 when duty cycles match Priority The pin is reset to 0 when a counter borrow occurs Because the constant output level mode is supported output can be maintained at a low or high level Polarity speci...

Page 325: ...R PCSR PCSR PDUT PDUT PDUT PCNH PCNH PCNH PCNL PCNL PCNL General control register 1 General control register 2 channel 0 timer register channel 0 cycle setting register channel 0 duty setting register channel 0 control status register channel 1 timer register channel 1 cycle setting register channel 1 duty cycle setting register channel 1 control status register channel 2 timer register channel 2 ...

Page 326: ...PWM timer channel General Block Diagram of PWM Timer Figure 14 2 1 General Block Diagram of PWM Timer PWM0 PWM1 4 PWM2 PWM3 16 bit reload timer ch0 16 bit reload timer ch1 General control register 2 External TRGs 0 to 3 General control register 1 source selection TRG input PWM timer ch0 TRG input PWM timer ch1 TRG input PWM timer ch2 TRG input PWM timer ch3 ...

Page 327: ... Figure 14 2 2 Block Diagram of Single PWM Timer Channel 1 1 cmp 1 4 ck 1 16 1 64 S Q R IRQ PCSR PDUT Prescaler Peripheral clock Load 16 bit decrementing counter Start Borrow PPG mask PWM output Inverse bit TRG input Enable Edge detection Software trigger interrupt selection ...

Page 328: ... 1 enables a software trigger A read instruction always reads 0 from this bit bit 13 MDSE Mode select bit This bit selects PWM operation that outputs continuous pulses or one shot operation that outputs a single pulse PCNH bit 15 14 13 12 11 10 9 8 Address ch0 0000E6H ch1 0000EEH CNTE STGR MDSE RTRG CKS1 CKS0 PGMS ch2 0000F6H ch3 0000FEH R W R W R W R W R W R W R W 0 0 0 0 0 0 0 PCNL bit 7 6 5 4 3...

Page 329: ...value to the cycle setting and duty cycle setting registers thereby inverting the output of the above mask values bit 8 Reserved bits 7 6 EGS1 SGS0 Trigger input edge select bits These bits select the edge applicable to the start source selected by general control register 1 In any edge mode setting the software trigger bit to 1 enables the software trigger 0 Disable restart Initial value 1 Enable...

Page 330: ...of the bit value bits 3 2 IRS1 IRS0 Interrupt cause select bit These bits select the cause that sets bit 4 IRQF bit 1 POEN PWM output enable bit Setting this bit to 1 enables PWM output bit 0 OSEL PWM output polarity specification bit This bit selects the polarity of PWM output This bit can be combined with bit 9 PGMS as shown below 0 Disabled initial value 1 Enabled Table 14 3 4 Selection of Inte...

Page 331: ...307 14 3 Control Status Register PCNH PCNL Polarity After resetting Duty cycle matching Counter borrow Normal polarity Output of L Inverse polarity Output of H ...

Page 332: ...PWM Cycle Setting Register PCSR The configuration of the PWM cycle setting register PCSR is shown below After the cycle setting register is initialized or rewritten write to the duty cycle setting register Use a 16 bit data instruction to access the cycle setting register PCSR bit 15 14 13 12 11 10 9 8 Address ch0 0000E2H ch1 0000EAH ch2 0000F2H ch3 0000FAH 7 6 5 4 3 2 1 0 Attribute Write only Ini...

Page 333: ...cle setting register PDUT is shown below When the same value is set in the cycle setting register and duty cycle setting register output is kept at a high level in normal polarity mode or output is kept at a low level in inverse polarity mode To ensure stable PWM output set values that make PCSR smaller than PDUT Use a 16 bit data instruction to access the cycle setting register PDUT bit 15 14 13 ...

Page 334: ...it decrementing counter PWM Timer Register PTMR The configuration of the PWM timer register PTMR is shown below Use a 16 bit data instruction to access the cycle setting register PTMR bit 15 14 13 12 11 10 9 8 Address ch0 0000E0H ch1 0000E8H ch2 0000F0H ch3 0000F8H 7 6 5 4 3 2 1 0 FFFFH Attribute Read only Initial value ...

Page 335: ...Configuration of General Control Register 1 GCN1 The configuration of the general control register 1 GCN1 is shown below GCN1 bit 15 14 13 12 11 10 9 8 Address 0000DCH TSEL33 30 TSEL23 20 R W R W R W R W R W R W R W R W 0 0 1 1 0 0 1 0 bit 7 6 5 4 3 2 1 0 TSEL13 10 TSEL03 00 R W R W R W R W R W R W R W R W 0 0 0 1 0 0 0 0 Attribute Attribute Initial value Initial value ...

Page 336: ... 16 bit reload timer channel 0 0 1 0 1 16 bit reload timer channel 1 0 1 1 X Reserved 1 0 0 0 External TRG0 1 0 0 1 External TRG1 1 0 1 0 External TRG2 1 0 1 1 External TRG3 1 1 X X Reserved Table 14 7 2 Selection of Ch2 Trigger Input TSEL23 20 ch2 trigger input 11 10 9 8 0 0 0 0 GCN2 EN0 bit 0 0 0 1 GCN2 EN1 bit Initial value 0 0 1 0 GCN2 EN2 bit 0 0 1 1 GCN2 EN3 bit 0 1 0 0 16 bit reload timer c...

Page 337: ...nnel 0 0 1 0 1 16 bit reload timer channel 1 0 1 1 X Setting prohibited 1 0 0 0 External TRG0 1 0 0 1 External TRG1 1 0 1 0 External TRG2 1 0 1 1 External TRG3 1 1 X X Reserved Table 14 7 4 Selection of Ch0 Trigger Input TSEL03 00 ch0 trigger input 3 2 1 0 0 0 0 0 GCN2 EN0 bit Initial value 0 0 0 1 GCN2 EN1 bit 0 0 1 0 GCN2 EN2 bit 0 0 1 1 GCN2 EN3 bit 0 1 0 0 16 bit reload timer channel 0 0 1 0 1...

Page 338: ... register is selected by the general control register 1 GCN1 the value of this register is transmitted as is to the PWM timer trigger input Multiple PWM timer channels can be activated simultaneously by making software generate the edge selected by the EGS1 and EGS0 bits of the control status register Always set bits 7 to 4 of this register to 0 GCN2 bit 7 6 5 4 3 2 1 0 Address 0000DFH EN3 EN2 EN1...

Page 339: ...G input is selected for the start trigger input pulses with a pulse width that equals or exceeds the following minimum pulse width Pulse width Two machine cycles or more When pulses that do not satisfy the condition above are input ensure that they are recognized as effective pulses Since this model has no filter function for external TRG input add a filter to the external input as required Figure...

Page 340: ... Figure 14 9 2 PWM Operation Timing Chart Trigger Restart Enabled m n 0 PWM Start trigger A rising edge is detected A trigger is ignored T Count clock cycle m PCSR value n PDUT value T n 1 T m 1 m n 0 PWM Start trigger A rising edge is detected T Count clock cycle m PCSR value n PDUT value T n 1 T m 1 PWM operation is restarted by a trigger ...

Page 341: ...on mode the PWM timer can output a single pulse of arbitrary width When an edge is detected during operation while restart is enabled the counter is reloaded Figure 14 10 1 shows a timing chart for one short operation performed while trigger restart is disabled Figure 14 10 2 shows a timing chart for one shot operation performed while trigger restart is enabled ...

Page 342: ...d Figure 14 10 2 One Shot Operation Timing Chart Trigger Restart Enabled m n 0 PWM Start trigger A rising edge is detected A trigger is ignored T Count clock cycle m PCSR value n PDUT value T n 1 T m 1 m n 0 PWM Start trigger A rising edge is detected T Count clock cycle m PCSR value n PDUT value T n 1 T m 1 Operation is restarted by a trigger ...

Page 343: ...es of Interrupts and Their Timing PWM Output Normal Polarity 0003 0002 0001 0000 0003 PWM Start trigger Load Clock Count value Interrupt Effective edge Duty cycle matching Counter borrow A maximum of 2 5T T count clock cycle is required until the count value is loaded after detection of a start trigger Up to 2 5T Effective edge ...

Page 344: ...utput at a Lower Level Example of keeping PWM output at a high level Figure 14 12 2 Example of Keeping PWM Output at a High Level PWM Decrease the duty value gradually An interrupt generated by a borrow causes 1 to be written to PGMS mask bit If an interrupt generated by a borrow causes 0 to be written to PGMS mask bit PWM waveforms can be output with no whisker PWM Increase the duty value gradual...

Page 345: ...e the GCN1 in the initial state because GCN2 is used in this example ch0 EN0 ch1 EN1 ch2 EN2 ch3 EN3 4 Set the control status register for the channels to be started as follows CNTE 1 Enable timer operation STGR 0 Leave this bit as is because GCN2 is used to issue a start trigger MDSE 0 PWM operation RTRG 0 Disable restart CSK1 0 00 Count clock φ PGMS 0 Do not mask output Bit 8 0 Unused bit Any va...

Page 346: ... select the 16 bit reload timer as the start trigger in GCN1 and then start the 16 bit reload timer instead of GCN2 in step 5 The PWM timer can be restarted at regular intervals by setting toggle output for the 16 bit reload timer by setting the following in the control status register RTRG 1 Enable restart EGS1 0 11 Start at both edges ...

Page 347: ...ations of the DMAC 15 1 Overview of DMAC 15 2 DMAC Parameter Descriptor Pointer DPDP 15 3 DMAC Control Status Register DACSR 15 4 DMAC Pin Control Register DATCR 15 5 Descriptor Register in RAM 15 6 DMAC Transfer Modes 15 7 Output of Transfer Request Acknowledgment and Transfer End signals 15 8 Notes on DMAC 15 9 DMAC Timing Charts ...

Page 348: ... 536 pulses Transfer end interrupt function Transfer address increment decrement selectable by software Three external transfer request input pins three external transfer request acknowledgment output pins and three external transfer end output pins DMAC Registers Figure 15 1 1 shows the DMAC registers Figure 15 1 1 DMAC Registers 31 0 00000200H DPDP 00000204H DACSR 00000208H DATCR 31 0 DPDP 0H DM...

Page 349: ...DMAC block diagram Figure 15 1 2 DMAC Block Diagram DPDP DACSR SADR DADR DATCR DACK0 2 EOP0 2 3 3 3 3 8 DREQ0 2 5 BLK DEC BLK DMACT INC DEC Edge level detection circuit Sequencer Internal resource transfer request Interrupt request Data buffer Switcher Mode Data bus ...

Page 350: ...n below This register is not initialized by resetting The register can be read and written Use a 32 bit transfer instruction to access the register Each descriptor that specifies the operation mode of each channel is placed at the address specified by the DPDP Table 15 2 1 lists the addresses at which individual descriptors are placed 31 7 6 0 00000200H 0000000 Initial value 0000000 Initial value ...

Page 351: ...tes that DMA transfer was interrupted because an error occurred in the DMA request source for the corresponding channel n 0 No error 1 An error occurred Error occurrence depnds on the DMA request source resource Errors do not occur in some DMA request sources 31 30 29 28 27 26 25 24 00000204H R W R W R W R W R W R W R W R W 23 22 21 20 19 18 17 16 R W R W R W R W R W R W R W R W 15 14 13 12 11 10 ...

Page 352: ... 29 25 21 17 13 9 5 1 DIEn DMA Operation Enable Each of these bits specifies whether to cause an interrupt request when DMA transfer is finished in the corresponding channel n when DEDn is 1 0 Do not cause an interrupt request 1 Cause an interrupt request These bits are initialized to 0 by resetting These bits can be both read and written bit 28 24 20 16 12 8 4 0 DOEn DMA Operation Enable Each of ...

Page 353: ...put pins and external transfer end output pins Configuration of DMAC Pin Control Register DATCR The configuration of the DMAC pin control register DATCR is shown below 31 24 00000208H 23 22 21 20 19 18 17 16 R W R W R W R W R W R W 15 14 13 12 11 10 9 8 R W R W R W R W R W R W 7 6 5 4 3 2 1 0 R W R W R W R W R W R W LS20 LS21 LS10 LS11 LS00 LS01 AKDE2 AKDE1 AKDE0 EPSE2 EPSE1 EPSE0 AKSE2 AKSE1 AKSE...

Page 354: ...ecify whether to enable the output function of the corresponding transfer request acknowledgment output signal pin These bits are initialized to 00 by resetting The bits can be both read and written bit 17 9 1 EPSEn Table 15 4 1 Selection of Transfer Input Detection Levels LSn1 LSn0 Operation control function 0 0 Detection of rising edge 0 1 Detection of falling edge 1 0 Detection of H level 1 1 D...

Page 355: ... are initialized to 00 by resetting The bits can be both read and written Table 15 4 3 Specification of Transfer End Output EPSEn EPDEn Operation control function 0 0 Disables transfer end output 0 1 Enables transfer end output Transfer end is output when transfer destination data is accessed 1 0 Transfer completion output enabled output when accessing the transfer source data access 1 1 Enables t...

Page 356: ...31 to 16 DMACT Transfer count These bits specify the number of times DMA transfer is to be performed When 0000H is specified DMA transfer is performed 65 536 times The value is decremented by 1 each time DMA transfer is performed bits 15 to 12 Reserved bits 11 to 8 BLK Block size specification These bits specify the size of blocks to be transferred in single block transfer mode When 0 is specified...

Page 357: ...f Transfer Source or Destination Address Update Modes SCS1 SCS0 DCS1 DCS0 Transfer source address Transfer destination address 0 0 0 0 Increment Increment 0 0 0 1 Increment Decrement 0 0 1 0 Increment Do not update 0 1 0 0 Decrement Increment 0 1 0 1 Decrement Decrement 0 1 1 0 Decrement Do not update 1 0 0 0 Do not update Increment 1 0 0 1 Do not update Decrement 1 0 1 0 Do not update Do not upda...

Page 358: ... When the transfer data size is a word specify an address consisting of a multiple of four Third Word of a Descriptor The third word contains the transfer destination address The address is updated at every transfer operation based on the address update mode specified by the DCS1 and DCS0 bits When the transfer data size is a halfword specify an address consisting of a multiple of two When the tra...

Page 359: ...rmation stored in the descriptor as many times as specified by BLK or until DMACT reaches 0 The DMAC outputs a transfer request acknowledgment signal during data transfer if external transfer request input is used When decremented DMACT reaches 0 the DMAC outputs a transfer end signal during data transfer 7 The DMAC clears the transfer request input 8 The DMAC increments or decrements SADR or DADR...

Page 360: ...fer end signal during data transfer 7 If the DMACT value is not 0 and a DMA request from a peripheral device remains the DMAC repeats step 6 via step 8 depending on the bus status 8 When the DMACT value is 0 or the DMA requests from peripheral devices are canceled the DMAC increments or decrements SADR or DADR and writes the result together with the DMACT value back to the descriptor 9 The DMAC re...

Page 361: ...fied by DMACT The DMAC outputs a transfer request acknowledgment signal during data transfer if external transfer request input is used When the decremented DMACT reaches 0 the DMAC outputs a transfer end signal during data transfer 7 The DMAC increments or decrements SADR or DADR and writes the result together with the DMACT value back to the descriptor 8 The DMAC returns the bus control right to...

Page 362: ...T counter is reset to 0 the transfer is ended and the DMAC outputs a transfer end signal Output of Transfer Request Acknowledgment Signal The transfer request acknowledgment signal is an active low pulse to be output after access to transfer data The AKSn and AKDn bits of the DATCR specify whether to output the signal synchronously with access to the transfer source or destination or both Output o...

Page 363: ...t is to be generated the DMAC operation enable bit in the DMAC must be set to disabled and the interrupt level must be set to an appropriate value Suppression of DMA Transfer for an Interrupt with a Higher Priority If during DMA transfer in response to a DMA transfer request an interrupt request with a higher priority arrives the MB91F109 can stop the DMA transfer HRCL register For stopping a DMA ...

Page 364: ... is set to interrupt inhibition level When the DMA transfer operation ends the CPU resumes execution of the next instruction after that during which sleep state was entered When performing a transfer operation while the CPU is in sleep state ensure through the design of the program that the CPU checks the appropriate conditions and enters again sleep state if required Control proceeds to the next ...

Page 365: ...A transfer is performed even if DREQ is canceled To prevent this select one of the following countermeasures Use DREQs in edge detection mode valid in block mode only Set the transfer destination address in the external area to generate a DACK during access to the transfer destination Set descriptors in external memory unless both transfer source and destination addresses are fixed ...

Page 366: ...descriptor No 0 0L Bit 15 to bit 0 of descriptor No 0 1 Descriptor No 1 1H Bit 31 to bit 16 of descriptor No 1 1L Bit 15 to bit 0 of descriptor No 1 2 Descriptor No 2 2H Bit 31 to bit 16 of descriptor No 2 2L Bit 15 to bit 0 of descriptor No 2 1 2 Descriptor No 1 or No 2 determined by SCS1 and SCS0 and DCS1 and DCS0 1 2H Bits 31 to 16 of Descriptor No 1 or 2 1 2L Bit 15 to bit 0 of descriptor No 1...

Page 367: ...e descriptor access block Descriptor Access Block Required pin input mode level descriptor address external Required pin input mode level descriptor address internal A CLK DREQn RDXD WRnX DACK EOP 2H 2H S S 1H 1L 1H 1L 0L 0H 0L 0H 2L 2L Addr pin Data pin A Interanl KB CLK DREQn Addr pin Data pin RDXD WRnX S S DACK EOP ...

Page 368: ...EQn is generated to when the DMAC operation starts shows the case where the DMAC operation starts first The DMAC operation may be delayed because the CPU fetches instructions and accesses data thereby creating bus contention A CLK DREQn RDXD WRnX 2H 2H S S 1H 1L 1H 1L 0L 0H 0L 0H 2L 2L Data pin Addr pin DACK EOP A CLK DREQn RDXD WRnX DACK EOP S S Addr pin Data pin ...

Page 369: ...ta Transfer Block for 16 Bit or 8 Bit Data Transfer source area external transfer destination area external Transfer source area external transfer destination area external RAM CLK DREQn Addr pin Data pin RDXD WRnX DACK EOP A W D D S 2 S 2 D D S S W D D S S W D D S S A CLK DREQn Addr pin Data pin RDXD WRnX DACK EOP S 2 S 2 S S S S S S ...

Page 370: ...346 CHAPTER 15 DMAC Transfer source area internal RAM transfer destination area external A CLK DREQn Addr pin Data pin RDXD WRnX DACK EOP 2 2 W D D D D D D D W W D W ...

Page 371: ...r source area external transfer destination area external Transfer source area external transfer destination area internal RAM Transfer source area internal RAM transfer destination area external CLK DREQn Addr pin Data pin RDXD WRnX DACK EOP W D D S S W 1 2L 1 2L 1 2H 1 2H W D D W W 0H 0H CLK DREQn Addr pin Data pin RDXD WRnX DACK EOP S S W 0H 0H S S W 1 2L 1 2H 1 2L 1 2H W CLK DREQn Addr pin Dat...

Page 372: ...al transfer destination area internal RAM Transfer source area internal RAM transfer destination area external CLK DREQn Addr pin Data pin RDXD WRnX DACK EOP W D D S S W 2L 2L 2H 2H W W D D W 0H 0H W 1L 1L 1H 1H W CLK DREQn Addr pin Data pin RDXD WRnX DACK EOP S S 0H 0H S S W W 2L 2L 2H 2H W W 1L 1L 1H 1H W CLK DREQn Addr pin Data pin RDXD WRnX DACK EOP W D D D D D D W W 0H 0H W W 2L 2L 2H 2H W W ...

Page 373: ...bits data length 8 16 bits Bus width 16 bits data length 32 bits CLK Addr pin Data pin RDXD WRnX AKSE 1 DACK AKDE 1 EPSE 1 EOP EPDE 1 W D D S S W 1 2L 1 2L 1 2H 1 2H W D D W W 0H 0H S S W D D Both are 1 Both are 1 CLK Addr pin Data pin RDXD WRnX AKSE 1 DACK AKDE 1 EPSE 1 EOP EPDE 1 SL SH SL SH W 1 2L 1 2L 1 2H 1 2H W DH DH W W 0H 0H DL DL W SL SH SL SH DH DH W DL DL W Both are 1 Both are 1 ...

Page 374: ...n Data pin RDXD WRnX AKSE 1 DACK AKDE 1 EPSE 1 EOP EPDE 1 W D D S S W 2L 2L 1H 1H W D D W W 0H 0H S S W D D W 1L 1L 2H 2H W Both are 1 Both are 1 CLK Addr pin Data pin RDXD WRnX AKSE 1 DACK AKDE 1 EPSE 1 EOP EPDE 1 CLK Addr pin Data pin RDXD WRnX SL SH SL SH W 1L 1L 1H 1H W DH DH W W 0H 0H DL DL W SL SH SL SH DH DH W DL DL W W 2L 2L 2H 2H W Both are 1 Both are 1 ...

Page 375: ... FR CPU For information on using the flash memory from the ROM writer refer to the user s guide for the ROM writer 16 1 Outline 16 2 Block Diagram of Flash Memory 16 3 Flash Memory Status Register FSTR 16 4 Sector Configuration of Flash Memory 16 5 Flash Memory Access Modes 16 6 Starting the Automatic Algorithm 16 7 Execution Status of the Automatic Algorithm ...

Page 376: ...atures equivalent to the features of the MBH29LV200 This enables high speed device operation Along with this manual refer to the MBM29LV200T 200B 10 12 15 Data Sheet Outline of Flash Memory The employed flash memory is an internal 254 kilobyte flash memory operated at 3 V The following features are implemented by combining flash memory macros and FR CPU interface circuits Features for use as CPU m...

Page 377: ...d of an automatic algorithm sequence that has continued for an extended period The RDYINT and INTE bits of the flash memory status register control the interrupt at the end of the automatic algorithm The RDYINT bit is an interrupt flag set at the end of the automatic algorithm When the rising edge of the internal Ready or Busy signal RDY BUSYX from 0 to 1 is detected the interrupt flag is set to 1...

Page 378: ...ram of Flash Memory Figure 16 2 1 Block diagram of the Flash Memory RDY BUSYX RESETX BYTEX OEX WEX CEX INTE RDYINT RDY WE FA18 0 DI15 0 DO31 0 CD31 0 CA18 0 2Mbit 254K 8 127K 16 Rising edge detection Control signal generation Flash memory Interrupt request Bus control signal Address buffer Data buffer FR C bus instruction data ...

Page 379: ...thm bit 6 RDYINT ReaDY INTerrupt The PDYINT bit is set to 1 when the automatic algorithm for a write erase operation etc in flash memory terminates When bit 7 INT 1 enables interrupt output and this bit bit 6 is set to 1 an interrupt request for terminating the automatic algorithm is generated After a reset the bit is initialized 0 Read Write operations for this bit are enabled However only write ...

Page 380: ...n status of the automatic algorithm write erase When this bit is 0 the automatic algorithm is executing a write or erase operation and another Write or Erase command cannot be accepted Data also cannot be read from an address in flash memory Reading this bit indicates the status of flash memory For details see Section 16 7 Execution Status of the Automatic Algorithm This bit is initialized to 0 du...

Page 381: ...ng for access from the CPU Figure 16 4 1 Memory Map and Sector Configuration SA4 16Kbyte SA3 8Kbyte SA2 8Kbyte SA1 32Kbyte SA0 63Kbyte SA5 63Kbyte SA6 32Kbyte SA7 8Kbyte SA8 8Kbyte SA9 16Kbyte 31 16 15 0 FFFFFFFFh RAM 1Kbyte RAM 1Kbyte 10000h 0C0800h 0FFFFC Dh 0F8000 1h 0F7FFC Dh 0F4000 1h 0F3FFF Dh 0F0000 1h 0EFFFC Dh 0E0000 1h 0DFFFC Dh 0C0800 1h 0C07FC Dh 0C0000 1h 0FFFFE Fh 0F8002 3h 0F7FFE Fh...

Page 382: ...bits bit 31 to 16 8 Kbyte SA3 000F4000 1h to 000F7FFC Dh MSB side 16 bits bit 31 to 16 8 Kbyte SA4 000F8000 1h to 000FFFFC Dh MSB side 16 bits bit 31 to 16 16 Kbyte SA5 000C0802 3h to 000DFFFE Fh LSB side 16 bits bit 15 to 0 63 Kbyte SA6 000E0002 3h to 000EFFFE Fh LSB side 16 bits bit 15 to 0 32 Kbyte SA7 000F0002 3h to 000F3FFE Fh LSB side 16 bits bit 15 to 0 8 Kbyte SA8 000F4002 3h to 000F7FFE F...

Page 383: ... FR CPU with no wait Restrictions Address assignment and endians in this mode differ from those for writing with the ROM writer In this mode commands and data cannot be written to flash memory together FR CPU Programming Mode 16 Bits Read Write This mode enables data to be written and erased As one word 32 bits cannot be accessed in one cycle program execution in flash memory is disabled in this m...

Page 384: ...ails on the automatic algorithm see Section 16 6 Starting the Automatic Algorithm Restrictions Address assignment and endians in this mode differ from those for writing with the ROM writer This mode inhibits reading data in words 32 bits ...

Page 385: ...t write cycle Second write cyc le Third write cycle Fourth write or read cyc le Fifth read cycle Sixt h write cyc le Data Data Data Data Data Data Read Reset 1 xxxxxxxxh F0F0h Read Reset 4 AAAAh 5555h F0F0h RA RD Program 4 AAAAh 5555h A0A0h PA PD Chip Erase 6 AAAAh 5555h 8080h AAAAh 1010h Sector Erase 6 AAAAh 5555h 8080h AAAAh SA 3030h Temporarily Stop Sector Erase B0B0h Start Sector Erase 3030h A...

Page 386: ... access cycles First two unlock cycles are executed then a Setup command is written After two more unlock cycles the Erase Chip command is entered During the Erase Chip command sequence the user does not have to write to flash memory before the erase operation When the automatic erase algorithm is executed flash memory checks cell states by writing a pattern of zeros before automatically erasing t...

Page 387: ... within the time out period waiting for time out ends and the erase operation is suspended The erase operation is restarted when a Restart Erase command was written Temporarily Stop Erase and Restart Erase commands can be entered with any address When a Temporarily Stop Erase command is entered during sector erase operation the flash memory needs a maximum of 20 µs to stop the erase operation When...

Page 388: ...When the value of the RDY bit is 0 the flash memory is executing a write or erase operation where new Write and Erase commands are not accepted When the value of the RDY bit is 1 the flash memory is in read write or erase operation wait state Hardware Sequence Flag For obtaining the hardware sequence flag as data read an arbitrary address an odd address in byte access from flash memory when the au...

Page 389: ...nce Flag Status DPOLL TOGGLE TLOVER SETIMR TOGGL2 Executing Automatic read operation Reverse data Toggle 0 0 1 Automatic erase operation 0 Toggle 0 1 Toggle Temporary erase stop mode Temporary erase stop and read from sectors in temporary erase stop 1 1 0 0 Toggle 1 Temporary erase stop and read from sectors not in temporary erase stop Data Data Data Data Data Temporary erase stop and write to sec...

Page 390: ...operation the toggle bit toggles for about 2 µs and stops to toggle without overwriting If all selected sectors are write protected the toggle bit toggles for about 100 µs and the system returns to the read mode without changing data Temporary sector erase stop status When a read operation is performed during a temporary sector erase stop operation flash memory outputs 1 if the address indicated b...

Page 391: ...erase operation flash memory outputs the data of bit 3 of the read value at the address indicated by the address signal bit 2 TOGGL2 Toggle bit Sector erase operation status Together with toggle bit 6 this toggle bit is used to indicate whether flash memory is subject to automatic erase operation or temporary erase stop operation If data is read consecutively from a sector that is subject to erasi...

Page 392: ...368 CHAPTER 16 FLASH MEMORY ...

Page 393: ...mming references concerning the I O maps interrupt vectors pin statuses in CPU states precautions on using the little endian area and instructions A I O Maps B Interrupt Vectors C Pin Status for Each CPU Status D Notes on Using Little Endian Areas E Instruction ...

Page 394: ...nitial value 1 0 Initial value 0 X Initial value X No register actually exists at this position Address Register Internal resource Port data register 0 1 2 3 000000H PDR3 R W XXXXXXXX PDR2 R W XXXXXXXX Read write attribute Initial register value after reset Register name the register listed in the first column is at address 4n the register listed in the second column is at address 4n 1 Leftmost re...

Page 395: ... R W 00 0 00 UART 0 000020H SSR R W 00001 00 SIDR R W XXXXXXXX SCR R W 00000100 SMR R W 00 0 00 UART 1 000024H SSR R W 00001 00 SIDR R W XXXXXXXX SCR R W 00000100 SMR R W 00 0 00 UART 2 000028H TMRLR W XXXXXXXX XXXXXXXX TMR W XXXXXXXX XXXXXXXX Reload Timer 0 00002CH TMCSR R W 0000 00000000 000030H TMRLR W XXXXXXXX XXXXXXXX TMR W XXXXXXXX XXXXXXXX Reload Timer 1 000034H TMCSR R W 0000 00000000 0003...

Page 396: ...eserved 000068H Reserved 00006CH Reserved 000070H 000074H Reserved 000078H UTIM UTIMR R W 00000000 00000000 UTIMC R W 0 00001 U Timer 0 0007CH UTIM UTIMR R W 00000000 00000000 UTIMC R W 0 00001 U Timer 1 000080H UTIM UTIMR R W 00000000 00000000 UTIMC R W 0 00001 U Timer 2 000084H Reserved 000088H 00008CH Reserved 000090H 000094H EIRR R W 00000000 ENIR R W 00000000 External interrupt NMI 000098H EL...

Page 397: ...0000B4H 0000B8H Table A 2 I O Map 2 6 Address Register Internal resource 0 1 2 3 Table A 3 I O Map 3 6 Address Register Internal resource 0 1 2 3 0000BCH Reserved 0000C0H 0000C4H 0000C8H 0000CCH 0000D0H DDRE W 00000000 DDRF W 00000000 Data direction register 0000D4H 0000D8H Reserved ...

Page 398: ...NL R W 00000000 0000F0H PTMR R 11111111 11111111 PCSR W XXXXXXXX XXXXXXXX 000F4H PDUT W XXXXXXXX XXXXXXXX PCNH R W 0000000 PCNL R W 00000000 0000F8H PTMR R 11111111 11111111 PCSR W XXXXXXXX XXXXXXXX 0000FCH PDUT W XXXXXXXX XXXXXXXX PCNH R W 0000000 PCNL R W 00000000 000100H to 0001FCH Reserved 000200H DPDP R W 0000000 DMAC 000204H DACSR R W 00000000 00000000 00000000 00000000 000208H DATCR R W XX0...

Page 399: ...0268H 00026CH 000270H 000274H 000278H to 0002FCH 000300H to 0003E3H Reserved 0003E4H Reserved 0003E8H Reserved 0003ECH 0003F0H BSD0 W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Bit search module 0003F4H BSD1 R W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0003F8H BSDC W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0003FCH BSRR R XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ...

Page 400: ...ICR16 R W 11111 ICR17 R W 11111 ICR18 R W 11111 ICR19 R W 11111 000414H ICR20 R W 11111 ICR21 R W 11111 ICR22 R W 11111 ICR23 R W 11111 000418H ICR24 R W 11111 ICR25 R W 11111 ICR26 R W 11111 ICR27 R W 11111 00041CH ICR28 R W 11111 ICR29 R W 11111 ICR30 R W 11111 ICR31 R W 11111 000420H 000424H 000428H 00042CH ICR47 R W 11111 000430H DICR R W 0 HRCL R W 11111 Delay interrupt 000434H to 00047CH Res...

Page 401: ...000000 00000010 AMR2 W 00000000 00000000 000614H ASR3 W 00000000 00000011 AMR3 W 00000000 00000000 000618H ASR4 W 00000000 00000100 AMR4 W 00000000 00000000 00061CH ASR5 W 00000000 00000101 AMR5 W 00000000 00000000 000620H AMD0 R W XX111 AMD1 R W 0 00000 AMD32 R W 00000000 AMD4 R W 0 00000 000624H AMD5 R W 0 00000 DSCR W 00000000 RFCR R W XXXXXX 00 000 000628H EPCR0 W 1100 1111111 EPCR0 W 1 111111...

Page 402: ...which a write only bit is set Data in areas marked as Reserved or is undefined RMW instructions RMW Read Modify Write AND Rj Ri OR Rj Ri EOR Rj Ri ANDH Rj Ri ORH Rj Ri EORH Rj Ri ANDB Rj Ri ORB Rj Ri EORB Rj Ri BANDL u4 Ri BORL u4 Ri BEORL u4 Ri BANDH u4 Ri BORH u4 Ri BEORH u4 Ri ...

Page 403: ...FFFECH Reserved for the system 5 05 3E8H 000FFFE8H Reserved for the system 6 06 3E4H 000FFFE4H Reserved for the system 7 07 3E0H 000FFFE0H Reserved for the system 8 08 3DCH 000FFFDCH Reserved for the system 9 09 3D8H 000FFFD8H Reserved for the system 10 0A 3D4H 000FFFD4H Reserved for the system 11 0B 3D0H 000FFFD0H Reserved for the system 12 0C 3CCH 000FFFCCH Reserved for the system 13 0D 3C8H 000...

Page 404: ...H 000FFF78H A D serial 34 22 ICR18 374H 000FFF74H Reload timer 0 35 23 ICR19 370H 000FFF70H Reload timer 1 36 24 ICR20 36CH 000FFF6CH Reload timer 2 37 25 ICR21 368H 000FFF68H Table B 1 Interrupt Vectors 1 2 Cause for the interrupt Interrupt No Interrupt level 1 Offset TBR default address 2 Decimal Hexa decimal Table B 2 Interrupt Vectors 2 2 Interrupt cause Interrupt number Interrupt level 1 Offs...

Page 405: ...the system 61 3D 308H 000FFF08H Reserved for the system 62 3E 304H 000FFF04H Delay interrupt cause bit 63 3F ICR47 300H 000FFF00H System reservation used by REALOS 3 64 40 2FCH 000FFEFCH System reservation used by REALOS 3 65 41 2F8H 000FFEF8H Used for INT instruction 66 to 255 42 to FF 2F4H to 000H 000FFEF4H to 000FFC00H Table B 2 Interrupt Vectors 2 2 Interrupt cause Interrupt number Interrupt l...

Page 406: ...fter the address indicated by the TBR is a vector address for EIT Each vector is 4 bytes in size The relationship between the vector number and vector address is as follows vctadr TBR vctofs TBR 3FCH 4 vct vctadr Vector address vctofs Vector offset vct Vector number ...

Page 407: ... Input functions are ready to use Input fixed to 0 External inputs are blocked out and the value 0 is transmitted internally from the input gate near the pin Output Hi Z Pin drive transistors are put in drive inhibited status and their pins are put in high impedance status Output retained The output status immediately before this mode is entered is output unchanged For example if an internal perip...

Page 408: ...tained P80 RDY P Previous status retained F RDY input P F Previous status retained P Previous status retained F RDY input P81 BGRNTX P Previous status retained F H output P F Previous status retained L output P82 BRQ P Previous status retained F BRQ input P F Previous status retained BRQ input RDX Previous status retained Previous status retained H output WR0X P85 WR1X P Previous status retained F...

Page 409: ...l setting Output Hi Z Input allowed for all pins PB1 CS0L PB2 CS0H PB3 DW0X PB4 RAS1 EOP2 Previous value retained PB5 CS1L DREQ2 Previous value retained PB6 CS1H DACK2 Previous value retained PB7 DW1X AN0 to AN3 AN0 3 Previous status retained Previous status retained PE0 to PE2 INT0 INT2 Input possible Input possible PE3 INT3 SC2 Previous status retained PE4 to PE5 DREQ0 DREQ1 PE6 to PE7 DACK0 DAC...

Page 410: ...5 SI2 OCPA1 PF6 SO2 OCPA2 PF7 OCPA0 ATGX Table C 2 Pin Status for 16 bit External Bus Length and 2CA1WR Mode Continued Pin name Function During sleep During stop Bus release BGRNT Reset time HIZX 0 HIZX 1 P when a general purpose port is specified F when the specified function is selected 1 Selfrefresh status is entered at selfrefresh start time When selfrefresh is cleared the previous value is re...

Page 411: ...P Previous status retained F RDY input P F Previous status retained P Previous status retained F RDY input P81 BGRNTX P Previous status retained F H output P F Previous status retained L output P82 BRQ P Previous status retained F BRQ input P F Previous status retained BRQ input RDX Previous status retained Previous status retained H output WR0X P85 WR1X P Previous status retained F H output P F P...

Page 412: ...l setting Output Hi Z Input allowed for all pins PB1 CS0L PB2 CS0H PB3 DW0X PB4 RAS1 EOP2 Previous value retained PB5 CS1L DREQ2 Previous value retained PB6 CS1H DACK2 Previous value retained PB7 DW1X AN0 to AN3 AN0 3 Previous status retained Previous status retained PE0 to PE2 INT0 INT2 Input possible Input possible PE3 INT3 SC2 Previous status retained PE4 to PE5 DREQ0 DREQ1 PE6 to PE7 DACK0 DAC...

Page 413: ...5 SI2 OCPA1 PF6 SO2 OCPA2 PF7 OCPA0 ATGX Table C 3 Pin Status for 16 bit External Bus Length and 2CA1WR Mode Continued Pin name Function During sleep During stop Bus release BGRNT Reset time HIZX 0 HIZX 1 P when a general purpose port is specified F when the specified function is selected 1 Selfrefresh status is entered at selfrefresh start time When selfrefresh is cleared the previous value is re...

Page 414: ...revious status retained P80 RDY P Previous status retained F RDY input P F Previous status retained P Previous status retained F RDY input P81 BGRNTX P Previous status retained F H output P F Previous status retained L output P82 BRQ P Previous status retained F BRQ input P F Previous status retained BRQ input RDX Previous status retained Previous status retained H output WR0X P85 Port Previous st...

Page 415: ...value retained 2 Same as left during refresh 1 PB4 RAS1 EOP2 Previous value retained PB5 CS1L DREQ2 Previous value retained PB6 CS1H P Previous status retained F Previous value retained P Previous status retained F Previous value retained Previous status retained DACK2 Previous value retained PB7 DW1X P Previous status retained F Previous value retained 2 Same as left during refresh 1 AN0 to AN3 A...

Page 416: ... TRG3 PF5 SI2 OCPA1 PF6 SO2 OCPA2 PF7 OCPA0 ATGX Table C 4 Pin Status in 8 bit External Bus Mode Continued Pin name Function During sleep During stop Bus release BGRNT Reset time HIZX 0 HIZX 1 P when a general purpose port is specified F when the specified function is selected 1 Selfrefresh status is entered at selfrefresh start time When selfrefresh is cleared the previous value is retained 2 Han...

Page 417: ... status retained Output Hi Z Input fixed to 0 Output Hi Z Input allowed for all pins P30 to P37 P40 to P47 P50 to P57 P60 to P67 P70 EOP0 P Previous status retained F EOP output P80 Port Previous status retained P81 P82 P83 P84 P85 PA0 PA1 to PA2 PA3 EOP1 P Previous status retained F EOP output PA4 to PA5 Port Previous status retained PA6 PB0 PB1 PB2 PB3 PB4 EOP2 P Previous status retained F EOP o...

Page 418: ...tained F DACK output PB7 Port Previous status retained AN0 to AN3 AN0 3 Previous status retained PE0 to PE2 INT0 INT2 Input possible Input possible PE3 INT3 SC2 PE4 to PE5 DREQ0 DREQ1 PE6 to PE7 DACK0 DACK1 PF0 SI0 TRG0 PF1 SO0 TRG1 PF2 SC0 OCPA3 PF3 SI1 TRG2 PF4 SO1 TRG3 PF5 SI2 OCPA1 PF6 SO2 OCPA2 PF7 OCPA0 ATGX Table C 5 Pin Status in Single Chip Mode Continued Pin name Function During sleep Du...

Page 419: ...le Endian Areas APPENDIX D Notes on Using Little Endian Areas This section contains notes on using little endian areas for each item below D 1 C Compiler fcc911 D 2 Assembler fasm911 D 3 Linker flnk911 D 4 Debugger sim911 eml1911 mon911 ...

Page 420: ...e endians While variables can be allocated to little endian areas their initial values cannot be set during assignment Set the initial values at the beginning of the program Example When setting an initial value for the variable little_data of the little endian area extern int little_data void little_init void little_data Initial value void main void little_init Assigning Structures by Referencing...

Page 421: ...sfer by memcpy The result of the above transfer is rendered incorrect by word data transfer as follows Specifying the Option K Lib when Using a Character String Manipulation Function When the K lib option is specified the compiler performs inline expansion for various character string manipulation functions In this case these functions may employ processing in half word or word units to optimize p...

Page 422: ...little big Transfer of double type data The execution result of the above transfer is rendered incorrect by the transfer of double type data as follows Allocating a Stack to a Little Endian Area If some part or the whole area of a stack is allocated to a little endian area the result of the subsequent operation may be rendered invalid 3f f0 00 00 00 00 00 00 Big endian area Little endian area Corr...

Page 423: ...n area is specified as data section storing a code or initial stack value the result of an access by the MB91F109 cannot be guaranteed Example Correct definition of endian area as a section SECTION Little_Area DATA ALIGN 4 Little_Word RES W 1 Little_Half RES H 1 Little_Byte RES B 1 Data Access When accessing data in a little endian area the data value can be coded independently of the endian area ...

Page 424: ... or LDH instruction STH r2 r3 8 bit data is accessed with a STB or LDB instruction STB r4 r5 If the MB91F109 accesses data with an operation for of a different size the data value cannot be guaranteed For example when two consecutive 16 bit data areas are simultaneously accessed using a 32 bit access instruction the data values cannot be assured ...

Page 425: ... can be allocated to little endian areas If data stack and code sections with initial values are allocated to little endian areas the result of subsequent operations cannot be guaranteed because operations such as resolving addresses are executed by the linker in big endian areas No Detection of Errors The linker outputs no error messages for allocations that violate the above restriction because ...

Page 426: ...ssed with the following commands an abnormal value is assumed set memory show memory enter examine set watch command When floating point data single double is handled the specified value cannot be set or displayed search memory command This command cannot search for half word and word data with the specified value line or reverse assemble including reverse assemble display of source window Normal ...

Page 427: ...nation of codes see Addressing mode codes 3 Indicates instruction formats 4 Operation codes are indicated by hexadecimal numbers 5 Indicates the number of machine cycles a Indicates memory access cycles that may be extended by the Ready function b Indicates memory access cycles that may be extended by the Ready function When the next instruction references a register subject to the LD operation in...

Page 428: ...IX E Instructions 6 Indicates flag changes 7 Indicates the operation for the instruction Flag change Changes Does not change Cleared Set C 0 1 C N Flag meaning Negative flag Zero flag Overflow flag Carry flag Z V ...

Page 429: ...2 Unsigned 32 bit immediate value 0X80000000 to 0XFFFFFFFF Note Values from 0X80000000 to 1 are handled as 0X80000000 to 0XFFFFFFFF s5 Signed 5 bit immediate value 16 to 15 s10 Signed 10 bit immediate value 512 to 508 multiple of 4 only u4 Unsigned 4 bit immediate value 0 to 15 u5 Unsigned 5 bit immediate value 0 to 31 u8 Unsigned 8 bit immediate value 0 to 255 u10 Unsigned 10 bit immediate value ...

Page 430: ...ddressing disp9 0X100 to 0XFE multiple of 2 only R14 disp8 Register using relative and indirect addressing disp8 0X80 to 0X7F R15 udisp6 Register using relative and indirect addressing udisp6 0 to 60 multiple of 4 only Ri Register using indirect addressing with postincrement R0 to R15 AC FP and SP R13 Register using indirect addressing with postincrement R13 AC SP Stack pop SP Stack push reglist R...

Page 431: ...ats Table E 2 Instruction Formats Type Instruction format A B C C D E MSB LSB 16bit OP Rj Ri 8 4 4 OP i8 o8 Ri 4 8 4 OP u4 m4 Ri 8 4 4 ADD ADDN CMP LSL LSR and ASR instructions only 7 5 4 OP Ri s5 u5 OP u8 rel8 dir reglist 8 8 OP SUB OP Ri 8 4 4 ...

Page 432: ...408 APPENDIX E Instructions F Table E 2 Instruction Formats OP rel11 5 11 ...

Page 433: ... or 16 32 Bit Immediate Value Transfer Instruction Table E 1 8 Memory Load Instructions Table E 1 9 Memory Store Instructions Table E 1 10 Interregister Transfer Instructions Table E 1 11 Standard Branch Without Delay Instructions Table E 1 12 Delayed Branch Instructions Table E 1 13 Other Instructions Table E 1 14 20 Bit Standard Branch Macro Instructions Table E 1 15 20 Bit Delayed Branch Macro ...

Page 434: ... Ri Addition with carry over ADDN Rj Ri ADDN s5 Ri ADDN i4 Ri ADDN2 i4 Ri A C C C A2 A0 A0 A1 1 1 1 1 Ri Rj Ri Ri s5 Ri Ri extu i4 Ri Ri extu i4 Ri Upper 1 bit is read as a code by the assembler Zero expansion Negative expansion SUB Rj Ri A AC 1 CCCC Ri Rj Ri SUBC Rj Ri A AD 1 CCCC Ri Rj c Ri Subtraction with carry over SUBN Rj Ri A AE 1 Ri Rj Ri Table E 1 2 Compare Operation Instructions Mnemonic...

Page 435: ...ycle NZVC Operation Remarks BANDL u4 Ri BANDH u4 Ri BAND u8 Ri 1 C C 80 81 1 2a 1 2a Ri 0xF0 u4 Ri u4 4 0x0FH Ri u8 Lower 4 bits are subject to operation Upper 4 bits are subject to operation BORL u4 Ri BORH u4 Ri BOR u8 Ri 2 C C 90 91 1 2a 1 2a Ri u4 Ri u4 4 Ri u8 Lower 4 bits are subject to operation Upper 4 bits are subject to operation BEORL u4 Ri BEORH u4 Ri BEOR u8 Ri 3 C C 98 99 1 2a 1 2a R...

Page 436: ... C C C C C MDL Ri MDL MDL Ri MDH MDL Ri MDL MDL Ri MDH Step operation 32bit 32bit 32bit 1 DIV0S DIV1 32 DIV2 DIV3 and DIV4S are created The instruction code length becomes 72 bytes 2 DIV0U and DIV1 32 are created The instruction code length becomes 66 bytes 3 Put a DIV3 instruction after the DIV2 instruction Table E 1 6 Shift Instructions Mnemonic Type OP Cycle NZVC Operation Remarks LSL Rj Ri LSL...

Page 437: ...o expanded Upper 24 bits are zero expanded When the immediate value is an absolute value the assembler automatically selects i8 i20 or i32 If the immediate value includes a relative value or external reference symbol i32 is selected Table E 1 8 Memory Load Instructions Mnemonic Type OP CYCLE NZVC Operation Remarks LD Rj Ri LD R13 Rj Ri LD R14 disp10 Ri LD R15 udisp6 Ri LD R15 Ri LD R15 Rs LD R15 P...

Page 438: ...i R15 ST Rs R15 ST PS R15 A A B C E E E 14 10 30 13 17 0 17 8 17 9 a a a a a a a Ri Rj Ri R13 Rj Ri R14 disp10 Ri R15 udisp6 R15 4 Ri R15 R15 4 Rs R15 R15 4 PS R15 Word Word Word Rs Special register STH Ri Rj STH Ri R13 Rj STH Ri R14 disp9 A A B 15 11 50 a a a Ri Rj Ri R13 Rj Ri R14 disp9 Half word Half word Half word STB Ri Rj STB Ri R13 Rj STB Ri R14 disp8 A A B 16 12 70 a a a Ri Rj Ri R13 Rj Ri...

Page 439: ...12 PC 2 PC PC 2 RP Ri PC RET E 97 2 2 RP PC Return INT u8 INTE D E 1F 9F 3 3 3a 3 3a SSP 4 PS SSP SSP 4 PC 2 SSP 0 I flag 0 S flag TBR 0x3FC u8 4 PC SSP 4 PS SSP SSP 4 PC 2 SSP 0 S flag TBR 0 3D8 PC For the emulator RETI E 97 3 2 2a CCCC R15 PC R15 4 R15 PS R15 4 BRA label9 BNO label9 BEQ label9 D D D E0 E1 E2 2 1 2 1 PC 2 label9 PC 2 PC Nonbranch if Z 1 then PC 2 label9 PC 2 PC BNE label9 BC labe...

Page 440: ...anch Instructions Mnemonic Type OP CYCLE NZVC Operation Remarks JMP D Ri E 9F 0 1 Ri PC CALL D label12 CALL D Ri F E D8 9F 1 1 1 PC 4 RP PC 2 label12 PC 2 PC PC 4 RP Ri PC RET D E 9F 2 1 RP PC Return BRA D label9 BNO D label9 BEQ D label9 D D D F0 F1 F2 1 1 1 PC 2 label9 PC 2 PC Nonbranch if Z 1 then PC 2 label9 PC 2 PC BNE D label9 BC D label9 BNC D label9 BN D label9 BP D label9 BV D label9 BNV ...

Page 441: ...STM reglist 3 D D 8E 8F R15 decrement reglist R15 R15 decrement Reglist R15 R15 decrement reglist R15 Multiple store R0 R7 Multiple store R8 R15 Multiple store R0 R15 ENTER u10 4 D 0F 1 a R14 R15 4 R15 4 R14 R15 u10 R15 Entrance processing of function LEAVE E 9F 9 b R14 4 R15 R15 4 R14 Exit processing of function XCHB Rj Ri A 8A 2a Ri TEMP Rj Ri TEMP Rj For semaphore management 1 The assembler con...

Page 442: ...V20 label20 Ri BNV20 label20 Ri BLT20 label20 Ri BGE20 label20 Ri BLE20 label20 Ri BGT20 label20 Ri BLS20 label20 Ri BHI20 label20 Ri s Z 0 s C 1 s C 0 s N 1 s N 0 s V 1 s V 0 s V xor N 1 s V xor N 0 s V xor N or Z 1 s V xor N or Z 0 s C or Z 1 s C or Z 0 Reference 1 CALL20 1 When label20 PC 2 is from 0x800 to 0x7fe an instruction is created as follows CALL label12 2 When label20 PC 2 is outside o...

Page 443: ...0 Ri BNV20 D label20 Ri BLT20 D label20 Ri BGE20 D label20 Ri BLE20 D label20 Ri BGT20 D label20 Ri BLS20 D label20 Ri BHI20 D label20 Ri s Z 0 s C 1 s C 0 s N 1 s N 0 s V 1 s V 0 s V xor N 1 s V xor N 0 s V xor N or Z 1 s V xor N or Z 0 s C or Z 1 s C or Z 0 Reference 1 CALL20 D 1 When label20 PC 2 is from 0x800 to 0x7fe an instruction is created as follows CALL D label12 2 When label20 PC 2 is o...

Page 444: ...el32 Ri BNV32 label32 Ri BLT32 label32 Ri BGE32 label32 Ri BLE32 label32 Ri BGT32 label32 Ri BLS32 label32 Ri BHI32 label32 Ri s Z 0 s C 1 s C 0 s N 1 s N 0 s V 1 s V 0 s V xor N 1 s V xor N 0 s V xor N or Z 1 s V xor N or Z 0 s C or Z 1 s C or Z 0 Reference 1 CALL32 1 When label32 PC 2 is from 0x800 to 0x7fe an instruction is created as follows CALL label12 2 When label32 PC 2 is outside of the r...

Page 445: ...2 Ri BNV32 D label32 Ri BLT32 D label32 Ri BGE32 D label32 Ri BLE32 D label32 Ri BGT32 D label32 Ri BLS32 D label32 Ri BHI32 D label32 Ri s Z 0 s C 1 s C 0 s N 1 s N 0 s V 1 s V 0 s V xor N 1 s V xor N 0 s V xor N or Z 1 s V xor N or Z 0 s C or Z 1 s C or Z 0 Reference 1 CALL32 D 1 When label32 PC 2 is from 0x800 to 0x7fe an instruction is created as follows CALL D label12 2 When label32 PC 2 is o...

Page 446: ...Operation Remarks DMOV dir10 R13 DMOV R13 dir10 DMOV dir10 R13 DMOV R13 dir10 DMOV dir10 R15 DMOV R15 dir10 D D D D D D 08 18 0C 1C 0B 1B b a 2a 2a 2a 2a dir10 R13 R13 dir10 dir10 R13 R13 4 R13 dir10 R13 4 R15 4 R15 dir10 R15 dir10 R15 4 Word Word Word Word Word Word DMOVH dir9 R13 DMOVH R13 dir9 DMOVH dir9 R13 DMOVH R13 dir9 D D D D 09 19 0D 1D b a 2a 2a dir9 R13 R13 dir9 dir9 R13 R13 2 R13 dir9 ...

Page 447: ...Command specification As this device type does not have coprocessors these instructions cannot be used Table E 1 20 Coprocessor Control Instructions Mnemonic Type OP CYCLE NZVC Operation Remarks COPOP u4 u8 CRj CRi COPLD u4 u8 Rj CRi COPST u4 u8 CRj Ri COPSV u4 u8 CRj Ri E E E E 9F C 9F D 9F E 9F F 2 a 1 2a 1 2a 1 2a Operation indication Rj CRi CRj Ri CRj Ri No error trap ...

Page 448: ...424 APPENDIX E Instructions ...

Page 449: ...425 INDEX INDEX The index follows on the next page This is listed in alphabetic order ...

Page 450: ...t function of 124 area mode register 32 AMD32 configuration of 124 area mode register 4 AMD4 bit function of 125 area mode register 4 AMD4 configuration of 125 area mode register 5 AMD5 bit function of 126 area mode register 5 AMD5 configuration of 126 area select register ASR and area mask register AMR configuration of 118 arithmetic operation 46 assembler source example of 109 asynchronous start...

Page 451: ...anged 348 continuous transfer mode for 16 8 bit data transfer stop in either address is unchanged 347 control register 236 control status register ADCS bit function of 270 control status register ADCS configuration of 270 control status register PCNH PCHL bit function of 304 control status register PCNH PCHL configuration of 304 control status register TMCSR bit function of 284 control status regi...

Page 452: ...AM interface 3 116 159 DRAM interface timing chart in high speed page mode 182 DRAM interface hyper 160 DRAM interface single 160 DRAM interface usual 160 DRAM refresh 161 DRAM signal control register DSCR bit function of 136 DRAM signal control register DSCR configuration of 136 E EIT cause 52 EIT characteristic 52 EIT event acceptance priority for 62 EIT vector table 60 EIT note on 53 EIT return...

Page 453: ...eria for determining 235 hold request cancel request interrupt level for 235 HRCL register 339 hyper DRAM interface read timing chart 188 hyper DRAM write timing chart 189 hyper DRAM interface timing chart 190 I I flag 55 I O circuit format 22 I O map 371 I O map how to read 370 I O port register 202 I O port basic block diagram of 202 immediate value setting or 16 31 bit immediate value transfer ...

Page 454: ...em into stop or sleep state 91 MB91F109 memory map 44 MB91F109 general block diagram of 6 MDH MDL 37 memory load instruction 413 memory map 24 memory map commen to FR series 45 memory store instruction 414 mode code addressing 405 mode data 70 mode pin 69 mode pin MD0 to MD2 27 mode register MODR 70 mode register MODR note on writing to 70 multiple PWM timer channel using 16 bit reload timer start...

Page 455: ...ng cause of 68 resetting initialization by 68 resource instruction 422 resource interrupt request as a DMA transfer request using 339 RETI instruction operation for 67 return point RP 37 RISC architecture 30 ROM writer writing by 353 row and column address 156 RSTX pin return by way of 93 S save restore processing 297 second word of descriptor 334 section 399 section type restriction on 401 sector...

Page 456: ...ing chart usual DRAM interface read 173 timing chart usual DRAM interface write 175 timing chart usual DRAM read cycle 177 timing chart usual DRAM write cycle 179 timing chart write cycle 168 TMCSR 284 transfer end signal output of 338 transfer mode burst 337 transfer mode continuous 336 transfer mode single block 335 transfer request acknowledgment signal output of 338 transfer stop in continuous...

Page 457: ...ay register WPR bit function of 85 watchdog timer reset delay register WPR configuration of 85 watchdog timer starting 99 word access 141 147 151 write cycle timing chart 168 write timing chart hyper DRAM interface 189 write timing chart single DRAM interface 186 writing by ROM writer 353 ...

Page 458: ...434 INDEX ...

Page 459: ...6 1E FUJITSU SEMICONDUCTOR CONTROLLER MANUALl FR30 32 Bit Microcontroller MB91F109 Hardware Manual February 2000 the first edition Published FUJITSU LIMITED Electronic Devices Edited Technical Communication Dept ...

Page 460: ......

Page 461: ...FUJITSU SEMICONDUCTOR FR30 32 Bit Microcontroller MB91F109 Hardware Manual ...

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