40
CHAPTER 2 CPU
[bit 3] N: Negative flag
This bit indicates a sign applicable when the operation result is assumed to be an integer
that is represented in two’s complement.
0: Indicates that the operation result is a positive value.
1: Indicates that the operation result is a negative value.
The initial value after resetting is undefined.
[bit 2] Z: Zero flag
This bit indicates whether the operation result is 0.
0: Indicates that the operation result is a value other than 0.
1: Indicates that the operation result is 0.
The initial value after resetting is undefined.
[bit 1] V: Overflow flag
This bit assumes that the operands used for operation are each an integer represented in
two’s complement and indicates whether an overflow occurred as the result of operation.
0: Indicates that no overflow occurred as the result of operation.
1: Indicates that an overflow occurred as the result of operation.
The initial value after resetting is undefined.
[bit 0] C: Carry flag
This bit indicates whether carry from the most significant bit or borrow occurred during
operation.
0: Indicates that no carry and borrow occurred.
1: Indicates that carry or borrow occurred.
The initial value after resetting is undefined.
❍
System condition code register (SCR)
The configuration of the system condition code register (SCR) is as follows:
[bit 10, 9] D1, D0: Step division flag
These bits hold intermediate data during execution of step division.
They must not be changed during execution of step division.
When other processing is performed during execution of step division, continued operation
for step division is guaranteed by saving and restoring the value in the PS register.
The initial value after resetting is undefined.
When the DIV0S instruction is executed, the dividend and divisor are referenced and set.
Execution of the DIV0U instruction forcibly clears the bits.
10
D1
D0
XX0
B
[Initial value]
T
9
8
Summary of Contents for MB91F109
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Page 96: ...72 CHAPTER 2 CPU ...
Page 224: ...200 CHAPTER 4 BUS INTERFACE ...
Page 234: ...210 CHAPTER 5 I O PORTS ...
Page 268: ...244 CHAPTER 9 U TIMER ...
Page 290: ...266 CHAPTER 10 UART ...
Page 314: ...290 CHAPTER 12 16 BIT RELOAD TIMER ...
Page 322: ...298 CHAPTER 13 BIT SEARCH MODULE ...
Page 392: ...368 CHAPTER 16 FLASH MEMORY ...
Page 432: ...408 APPENDIX E Instructions F Table E 2 Instruction Formats OP rel11 5 11 ...
Page 448: ...424 APPENDIX E Instructions ...
Page 449: ...425 INDEX INDEX The index follows on the next page This is listed in alphabetic order ...
Page 458: ...434 INDEX ...
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