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CHAPTER 15 DMAC
[bits 1, 0] MOD1, MOD0: Transfer mode
These bits specify the transfer mode.
The continuous transfer mode can be used for channels 0 to 2 only.
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Second Word of a Descriptor
The second word contains the transfer source address.
The address is updated at every transfer operation based on the address update mode
specified by the SCS1 and SCS0 bits.
When the transfer data size is halfword, specify an address consisting of a multiple of two.
When the transfer data size is a word, specify an address consisting of a multiple of four.
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Third Word of a Descriptor
The third word contains the transfer destination address.
The address is updated at every transfer operation based on the address update mode
specified by the DCS1 and DCS0 bits.
When the transfer data size is a halfword, specify an address consisting of a multiple of two.
When the transfer data size is a word, specify an address consisting of a multiple of four.
Table 15.5-4 Transfer Mode Specification
MOD1
MOD0
Operation mode
0
0
Single/block mode
0
1
Burst mode
1
0
Continuos transfer mode
1
1
Reserved
31
0
R/W
SADR
31
0
R/W
DADR
Summary of Contents for MB91F109
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Page 96: ...72 CHAPTER 2 CPU ...
Page 224: ...200 CHAPTER 4 BUS INTERFACE ...
Page 234: ...210 CHAPTER 5 I O PORTS ...
Page 268: ...244 CHAPTER 9 U TIMER ...
Page 290: ...266 CHAPTER 10 UART ...
Page 314: ...290 CHAPTER 12 16 BIT RELOAD TIMER ...
Page 322: ...298 CHAPTER 13 BIT SEARCH MODULE ...
Page 392: ...368 CHAPTER 16 FLASH MEMORY ...
Page 432: ...408 APPENDIX E Instructions F Table E 2 Instruction Formats OP rel11 5 11 ...
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Page 449: ...425 INDEX INDEX The index follows on the next page This is listed in alphabetic order ...
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