Freescale Semiconductor MC9S08PT60, Reference Manual

Page: 163 / 679

PORT_PTAD field descriptions (continued)
Field Description
Reset forces PTAD to all 0s, but these 0s are not driven out of the corresponding pins because reset also
configures all port pins as high-impedance inputs with pullups disabled.
7.7.2 Port B Data Register (PORT_PTBD)
Address: 0h base + 1h offset = 1h
Bit 7 6 5 4 3 2 1 0
Read
PTBD
Write
Reset 0 0 0 0 0 0 0 0
PORT_PTBD field descriptions
Field Description
PTBD Port B Data Register Bits
For port B pins that are configured as inputs, a read returns the logic level on the pin.
For port B pins that are configured as outputs, a read returns the last value that was written to this register.
For port B pins that are configured as Hi-Z, a read returns uncertainty data.
Writes are latched into all bits of this register. For port B pins that are configured as outputs, the logic level
is driven out of the corresponding MCU pin.
Reset forces PTBD to all 0s, but these 0s are not driven out of the corresponding pins because reset also
configures all port pins as high-impedance inputs with pullups disabled.
7.7.3 Port C Data Register (PORT_PTCD)
Address: 0h base + 2h offset = 2h
Bit 7 6 5 4 3 2 1 0
Read
PTCD
Write
Reset 0 0 0 0 0 0 0 0
PORT_PTCD field descriptions
Field Description
PTCD Port C Data Register Bits
For port C pins that are configured as inputs, a read returns the logic level on the pin.
For port C pins that are configured as outputs, a read returns the last value that was written to this
register.
For port C pins that are configured as Hi-Z, a read returns uncertainty data.
Writes are latched into all bits of this register. For port C pins that are configured as outputs, the logic level
is driven out of the corresponding MCU pin.
Chapter 7 Parallel input/output
MC9S08PT60 Reference Manual, Rev. 4, 08/2014
Freescale Semiconductor, Inc. 163