Freescale Semiconductor MC9S08PT60, Reference Manual

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ICS_S field descriptions (continued)
Field Description
Stop mode entry will also cause the lock status bit to clear and stay cleared until the FLL has reacquired
lock.
NOTE: Wait at least for Tqcquire after wake from stop mode to start timing critical tasks like serial
communication. Do not need to wait for LOCK bit to set after wake from stop mode.
0 FLL is currently unlocked.
1 FLL is currently locked.
5
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
4
IREFST
Internal Reference Status
The IREFST bit indicates the current source for the reference clock. The IREFST bit does not update
immediately after a write to the IREFS bit due to internal synchronization between clock domains.
0 Source of reference clock is external clock.
1 Source of reference clock is internal clock.
3–2
CLKST
Clock Mode Status
The CLKST bits indicate the current clock mode. The CLKST bits don't update immediately after a write to
the CLKS bits due to internal synchronization between clock domains.
00 Output of FLL is selected.
01 FLL Bypassed, internal reference clock is selected.
10 FLL Bypassed, external reference clock is selected.
11 Reserved.
Reserved This field is reserved.
This read-only field is reserved and always has the value 0.
8.6.6 OSC Status and Control Register (ICS_OSCSC)
Address: 3038h base + 6h offset = 303Eh
Bit 7 6 5 4 3 2 1 0
Read
OSCEN
0
OSCSTEN OSCOS
0
RANGE HGO
OSCINIT
Write
Reset 0 0 0 0 0 0 0 0
ICS_OSCSC field descriptions
Field Description
7
OSCEN
OSC Enable
The OSCEN bit enables the external clock for use as ICSERCLK.
0 OSC module disabled.
1 OSC module enabled.
Table continues on the next page...
Chapter 8 Clock management
MC9S08PT60 Reference Manual, Rev. 4, 08/2014
Freescale Semiconductor, Inc. 221