Freescale Semiconductor MC9S08PT60, Reference Manual

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SWSYNC bit
system clock
PWM synchronization
software trigger event
write 1 to SWSYNC bit
Figure 12-224. Software Trigger event
12.4.11.3 Boundary cycle
The CNTMAX and CNTMIN bits select the boundary cycle when the MODH:L and
CnVH:L registers are updated with the value of their write buffer by PWM
synchronization, except if (PWMSYNC = 0 and REINIT = 1).
If CNTMIN = 1, then the boundary cycle is the CNTINH:L value. MODH:L and
CnVH:L registers are updated when the FTM counter reaches the CNTINH:L value. If
CPWMS = 0, then CNTINH:L is reached when the FTM counter changes from MODH:L
to CNTINH:L. If CPWMS = 1, then CNTINH:L is reached when the FTM counter
changes from (CNTINH:L + 0x0001) to CNTINH:L.
If CNTMAX = 1, then the boundary cycle is the MODH:L value. MODH:L and CnVH:L
registers are updated when the FTM counter reaches the MODH:L value. MODH:L is
reached when the FTM counter changes from (MODH:L – 0x0001) to MODH:L,
regardless of the CPWMS configuration.
If no boundary cycle was selected (CNTMAX = 0 and CNTMIN = 0), then the update of
the MODH:L and CnVH:L registers is not made, unless (PWMSYNC = 0 and REINIT =
1).
If both boundary cycles were selected (CNTMAX = 1 and CNTMIN = 1), then the
update of the MODH:L and CnVH:L registers is made in the first boundary cycle that
occurs with valid conditions for MODH:L or CnVH:L synchronization, except if
(PWMSYNC = 0 and REINIT = 1).
The CNTMAX and CNTMIN bits are cleared only by software.
Functional Description
MC9S08PT60 Reference Manual, Rev. 4, 08/2014
362 Freescale Semiconductor, Inc.