Freescale Semiconductor MC9S08PT60, Reference Manual

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18.3.6 I2C Control Register 2 (I2C_C2)
Address: 3070h base + 5h offset = 3075h
Bit 7 6 5 4 3 2 1 0
Read
GCAEN ADEXT
0 0
RMEN AD[10:8]
Write
Reset 0 0 0 0 0 0 0 0
I2C_C2 field descriptions
Field Description
7
GCAEN
General Call Address Enable
Enables general call address.
0 Disabled
1 Enabled
6
ADEXT
Address Extension
Controls the number of bits used for the slave address.
0 7-bit address scheme
1 10-bit address scheme
5
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
3
RMEN
Range Address Matching Enable
This bit controls the slave address matching for addresses between the values of the A1 and RA registers.
When this bit is set, a slave address matching occurs for any address greater than the value of the A1
register and less than or equal to the value of the RA register.
0 Range mode disabled. No address matching occurs for an address within the range of values of the
A1 and RA registers.
1 Range mode enabled. Address matching occurs when a slave receives an address within the range of
values of the A1 and RA registers.
AD[10:8] Slave Address
Contains the upper three bits of the slave address in the 10-bit address scheme. This field is valid only
while the ADEXT bit is set.
18.3.7 I2C Programmable Input Glitch Filter Register (I2C_FLT)
Address: 3070h base + 6h offset = 3076h
Bit 7 6 5 4 3 2 1 0
Read
Reserved
0
FLT
Write
Reset 0 0 0 0 0 0 0 0
Memory map/register definition
MC9S08PT60 Reference Manual, Rev. 4, 08/2014
516 Freescale Semiconductor, Inc.