Freescale Semiconductor MC9S08PT60, Reference Manual

Page: 223 / 679

8.7.1 System Clock Gating Control 1 Register (SCG_C1)
This high page register contains control bits to enable or disable the bus clock to the
FTMs, MTIMs, and RTC modules. Gating off the clocks to unused peripherals is used to
reduce the MCU's run and wait currents.
NOTE
User software should disable the peripheral before disabling the
clocks to the peripheral. When clocks are re-enabled to a
peripheral, the peripheral registers need to be re-initialized by
user software.
Address: 300Ch base + 0h offset = 300Ch
Bit 7 6 5 4 3 2 1 0
Read
FTM2 FTM1 FTM0
0
MTIM1 MTIM0 RTC
Write
Reset 1 1 1 0 0 1 1 1
SCG_C1 field descriptions
Field Description
7
FTM2
FTM2 Clock Gate Control
This bit controls the clock gate to the FTM2 module.
0 Bus clock to the FTM2 module is disabled.
1 Bus clock to the FTM2 module is enabled.
6
FTM1
FTM1 Clock Gate Control
This bit controls the clock gate to the FTM1 module.
0 Bus clock to the FTM1 module is disabled.
1 Bus clock to the FTM1 module is enabled.
5
FTM0
FTM0 Clock Gate Control
This bit controls the clock gate to the FTM0 module.
0 Bus clock to the FTM0 module is disabled.
1 Bus clock to the FTM0 module is enabled.
4–3
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
2
MTIM1
MTIM1 Clock Gate Control
This bit controls the clock gate to the MTIM1 module.
0 Bus clock to the MTIM1 module is disabled.
1 Bus clock to the MTIM1 module is enabled.
1
MTIM0
MTIM0 Clock Gate Control
Table continues on the next page...
Chapter 8 Clock management
MC9S08PT60 Reference Manual, Rev. 4, 08/2014
Freescale Semiconductor, Inc. 223