PORT_PTHIE field descriptions (continued)
Field
Description
5–3
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
2
PTHIE2
Input Enable for Port H Bit 2
This read/write bit enables the port H pin as an input.
0
Input disabled for port H bit 2.
1
Input enabled for port H bit 2.
1
PTHIE1
Input Enable for Port H Bit 1
This read/write bit enables the port H pin as an input.
0
Input disabled for port H bit 1.
1
Input enabled for port H bit 1.
0
PTHIE0
Input Enable for Port H Bit 0
This read/write bit enables the port H pin as an input.
0
Input disabled for port H bit 0.
1
Input enabled for port H bit 0.
7.7.26 Port Filter Register 0 (PORT_IOFLT0)
This register sets the filters for input from PTA to PTD.
Address: 0h base + 30ECh offset = 30ECh
Bit
7
6
5
4
3
2
1
0
Read
Write
Reset
0
0
0
0
0
0
0
0
PORT_IOFLT0 field descriptions
Field
Description
7–6
FLTD
Filter selection for input from PTD
00
BUSCLK
01
FLTDIV1
10
FLTDIV2
11
FLTDIV3
5–4
FLTC
Filter selection for input from PTC
00
BUSCLK
01
FLTDIV1
10
FLTDIV2
11
FLTDIV3
Table continues on the next page...
Port data registers
MC9S08PT60 Reference Manual, Rev. 4, 08/2014
186
Freescale Semiconductor, Inc.
Summary of Contents for MC9S08PT60
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