Freescale Semiconductor MC9S08PT60, Reference Manual

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SCG_C1 field descriptions (continued)
Field Description
This bit controls the clock gate to the MTIM0 module.
0 Bus clock to the MTIM0 module is disabled.
1 Bus clock to the MTIM0 module is enabled.
0
RTC
RTC Clock Gate Control
This bit controls the clock gate to the RTC module.
0 Bus clock to the MTRTCIM1 module is disabled.
1 Bus clock to the RTC module is enabled.
8.7.2 System Clock Gating Control 2 Register (SCG_C2)
This high-page register contains control bits to enable or disable the bus clock to the
DBG, NVM, CRC, and IPC modules. Gating off the clocks to unused peripherals is used
to reduce the MCU's run and wait currents.
NOTE
User software should disable the peripheral before disabling the
clocks to the peripheral. When clocks are re-enabled to a
peripheral, the peripheral registers need to be re-initialized by
user software.
Address: 300Ch base + 1h offset = 300Dh
Bit 7 6 5 4 3 2 1 0
Read 0
DBG NVM IPC CRC
0
Write
Reset 0 0 1 1 1 1 0 0
SCG_C2 field descriptions
Field Description
7–6
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
5
DBG
DBG Clock Gate Control
This bit controls the clock gate to the DBG module.
0 Bus clock to the DBG module is disabled.
1 Bus clock to the DBG module is enabled.
4
NVM
NVM Clock Gate Control
This bit controls the clock gate to the NVM module.
Table continues on the next page...
System clock gating control registers
MC9S08PT60 Reference Manual, Rev. 4, 08/2014
224 Freescale Semiconductor, Inc.