Freescale Semiconductor MC9S08PT60, Reference Manual

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ADC_SC3 field descriptions (continued)
Field Description
01 10-bit conversion (N=10)
10 12-bit conversion (N=12)
11 Reserved
ADICLK Input Clock Select
ADICLK bits select the input clock source to generate the internal clock ADCK.
00 Bus clock
01 Bus clock divided by 2
10 Alternate clock (ALTCLK)
11 Asynchronous clock (ADACK)
19.3.4 Status and Control Register 4 (ADC_SC4)
This register controls the FIFO scan mode, FIFO compare function and FIFO depth
selection of the ADC module.
Address: 10h base + 3h offset = 13h
Bit 7 6 5 4 3 2 1 0
Read 0
ASCANE ACFSEL
0
AFDEP
Write
Reset
0 0 0 0 0 0 0 0
ADC_SC4 field descriptions
Field Description
7
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
6
ASCANE
FIFO Scan Mode Enable
The FIFO always use the first dummied FIFO channels when it is enabled. When this bit is set and FIFO
function is enabled, ADC will repeat using the first FIFO channel as the conversion channel until the result
FIFO is fulfilled. In continuous mode (ADCO = 1), ADC will start next conversion with the same channel
when COCO is set.
0 FIFO scan mode disabled.
1 FIFO scan mode enabled.
5
ACFSEL
Compare function select OR/AND when the FIFO function is enabled (AFDEP > 0). When this field is
cleared, ADC will OR all of compare triggers and set COCO after at least one of compare trigger occurs.
When this field is set, ADC will AND all of compare triggers and set COCO after all of compare triggers
occur.
0 OR all of compare trigger.
1 AND all of compare trigger.
4–3
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
Table continues on the next page...
ADC Control Registers
MC9S08PT60 Reference Manual, Rev. 4, 08/2014
544 Freescale Semiconductor, Inc.