TRIG0 bit
system clock
selected boundary cycle
MODH:L registers
are updated if both bytes
were written
trigger 0 event
write 1 to TRIG0 bit
Figure 12-226. MODH:L synchronization when (PWMSYNC = 0), (REINIT = 0), and a
hardware trigger was used
• If PWMSYNC = 0 and REINIT = 1, then the synchronization is made on the next
enabled trigger event. If the trigger event was a software trigger, then the SWSYNC
bit is cleared. See the following figure.
SWSYNC bit
system clock
MODH:L registers
are updated if both bytes
were written
software trigger event
write 1 to SWSYNC bit
Figure 12-227. MODH:L synchronization when (PWMSYNC = 0), (REINIT = 1), and
software trigger was used
If the trigger event was a hardware trigger, then the TRIGn bit is cleared. See the
following figure.
Functional Description
MC9S08PT60 Reference Manual, Rev. 4, 08/2014
364
Freescale Semiconductor, Inc.
Summary of Contents for MC9S08PT60
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