12.3.9 Channel Value High (FTMx_CnVH)
These registers contain the captured FTM counter value of the input capture function or
the match value for the output modes.
In input capture, capture test, and dual edge capture modes, reading a single byte in CnV
latches the contents into a buffer where they remain latched until the other byte is read.
This latching mechanism also resets, or becomes unlatched, when the CnSC register is
written whether BDM mode is active or not. Any write to the channel registers is ignored
during these input modes.
When BDM is active, the read coherency mechanism is frozen such that the buffer
latches remain in the state they were in when the BDM became active, even if one or both
bytes of the channel value register are read while BDM is active. This ensures that if you
were in the middle of reading a 16-bit register when BDM became active, it reads the
appropriate value from the other half of the 16-bit value after returning to normal
execution. Any read of the CnV registers in BDM mode bypasses the buffer latches and
returns the value of these registers and not the value of their read buffer.
In output modes, writing to CnV latches the value into a buffer. The registers are updated
with the value of their write buffer according to
Update of the registers with write
.
If MODE[FTMEN] = 0, this write coherency mechanism may be manually reset by
writing to the CnSC register whether BDM mode is active or not. This latching
mechanism allows coherent 16-bit writes in either big-endian or little-endian order, which
is friendly to various compiler implementations.
When BDM is active, the write coherency mechanism is frozen such that the buffer
latches remain in the state they were in when the BDM became active even if one or both
bytes of the channel value register are written while BDM is active. Any write to the CnV
registers bypasses the buffer latches and writes directly to the register while BDM is
active. The values written to the channel value registers while BDM is active are used in
output modes operation after normal execution resumes. Writes to the channel value
registers while BDM is active do not interfere with the partial completion of a coherency
sequence. After the write coherency mechanism has been fully exercised, the channel
value registers are updated using the buffered values while BDM was not active.
Address: Base a 6h (3d × i), where i=0d to 5d
Bit
7
6
5
4
3
2
1
0
Read
Write
Reset
0
0
0
0
0
0
0
0
Chapter 12 FlexTimer Module (FTM)
MC9S08PT60 Reference Manual, Rev. 4, 08/2014
Freescale Semiconductor, Inc.
315
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