FTMx_SYNC field descriptions (continued)
Field
Description
0
External trigger 0 is not selected.
1
External trigger 0 is selected.
3
SYNCHOM
Output Mask Synchronization
Selects when the CHnOM bits in register OUTMASK are updated with the value of their write buffer.
0
CHnOM bits are updated with the value of the OUTMASK write buffer in all rising edges of the system
clock.
1
CHnOM bits are updated with the value of the OUTMASK write buffer only by the PWM
synchronization.
2
REINIT
FTM Counter Reinitialization by Synchronization (See “FTM Counter Synchronization”)
Determines if the FTM counter is reinitialized when the selected trigger for the synchronization is detected.
0
FTM counter continues to count normally.
1
FTM counter is updated with its initial value when the selected trigger is detected.
1
CNTMAX
Maximum Boundary Cycle Enable
Determines when the MOD, CNTIN, and CV registers are updated with their write buffer contents following
a PWM synchronization event. If CNTMAX is enabled, the registers are updated when the FTM counter
reaches its maximum value MOD.
0
The maximum boundary cycle is disabled.
1
The maximum boundary cycle is enabled.
0
CNTMIN
Minimum Boundary Cycle Enable
Determines when the MOD and CV registers are updated with their write buffer contents after a PWM
synchronization event. If CNTMIN is enabled, the registers are updated when the FTM counter reaches its
minimum value CNTIN.
0
The minimum boundary cycle is disabled.
1
The minimum boundary cycle is enabled.
12.3.16 Initial State for Channel Output (FTMx_OUTINIT)
Address: Base a 1Ch offset
Bit
7
6
5
4
3
2
1
0
Read
Write
Reset
0
0
0
0
0
0
0
0
FTMx_OUTINIT field descriptions
Field
Description
7
CH7OI
Channel 7 Output Initialization Value
Selects the value that is forced into the channel output when the initialization occurs.
Table continues on the next page...
Memory map and register definition
MC9S08PT60 Reference Manual, Rev. 4, 08/2014
322
Freescale Semiconductor, Inc.
Summary of Contents for MC9S08PT60
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