Freescale Semiconductor MC9S08PT60, Reference Manual

Page: 475 / 679

17.3 Memory map/register definition
The SPI has 8-bit registers to select SPI options, to control baud rate, to report SPI status,
to hold an SPI data match value, and for transmit/receive data.
SPI memory map
Address
offset (hex)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
0 30A0 SPI Control Register 1 (SPI1_C1) 8 R/W 04h 17.3.1/475
1 30A1 SPI Control Register 2 (SPI1_C2) 8 R/W 00h 17.3.2/477
2 30A2 SPI Baud Rate Register (SPI1_BR) 8 R/W 00h 17.3.3/478
3 30A3 SPI Status Register (SPI1_S) 8 R 20h 17.3.4/479
4 30A4 SPI data register high (SPI1_DH) 8 R/W 00h 17.3.5/482
5 30A5 SPI Data Register low (SPI1_DL) 8 R/W 00h 17.3.6/483
6 30A6 SPI match register high (SPI1_MH) 8 R/W 00h 17.3.7/484
7 30A7 SPI Match Register low (SPI1_ML) 8 R/W 00h 17.3.8/484
8 30A8 SPI control register 3 (SPI1_C3) 8 R/W 00h 17.3.9/485
9 30A9 SPI clear interrupt register (SPI1_CI) 8 R/W 00h 17.3.10/486
17.3.1 SPI Control Register 1 (SPIx_C1)
This read/write register includes the SPI enable control, interrupt enables, and
configuration options.
Address: 30A0h base + 0h offset = 30A0h
Bit 7 6 5 4 3 2 1 0
Read
SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE
Write
Reset
0 0 0 0 0 1 0 0
SPI1_C1 field descriptions
Field Description
7
SPIE
SPI Interrupt Enable: for SPRF and MODF (when FIFO is not supported or not enabled) or for read FIFO
(when FIFO is supported and enabled)
When the FIFO is not supported or not enabled (FIFOMODE is not present or is 0): Enables the interrupt
for SPI receive buffer full (SPRF) and mode fault (MODF) events.
Table continues on the next page...
Chapter 17 16-Bit Serial Peripheral Interface (16-Bit SPI)
MC9S08PT60 Reference Manual, Rev. 4, 08/2014
Freescale Semiconductor, Inc. 475