Freescale Semiconductor MC9S08PT60, Reference Manual

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SPI1_S field descriptions (continued)
Field Description
type of reset occurs and FIFOMODE is 0, TNEAREF and RFIFOEF continue to reset to 0. If this
type of reset occurs and FIFOMODE is 1, TNEAREF and RFIFOEF reset to 1.
0 Transmit FIFO has more than 16 bits (when C3[5] is 0) or more than 32 bits (when C3[5] is 1)
remaining to transmit
1 Transmit FIFO has an amount of data equal to or less than 16 bits (when C3[5] is 0) or 32 bits (when
C3[5] is 1) remaining to transmit
1
TXFULLF
Transmit FIFO full flag
This bit indicates the status of the transmit FIFO when FIFOMODE is enabled. This flag is set when there
are 8 bytes in the transmit FIFO. If FIFOMODE is not enabled, ignore this bit.
0 Transmit FIFO has less than 8 bytes
1 Transmit FIFO has 8 bytes of data
0
RFIFOEF
SPI read FIFO empty flag
This bit indicates the status of the read FIFO when FIFOMODE is enabled. If FIFOMODE is not enabled,
ignore this bit.
NOTE: At an initial POR, the values of TNEAREF and RFIFOEF are 0. However, the status (S) register
and both TX and RX FIFOs are reset due to a change of SPIMODE, FIFOMODE or SPE. If this
type of reset occurs and FIFOMODE is 0, TNEAREF and RFIFOEF continue to reset to 0. If this
type of reset occurs and FIFOMODE is 1, TNEAREF and RFIFOEF reset to 1.
0 Read FIFO has data. Reads of the DH:DL registers in 16-bit mode or the DL register in 8-bit mode will
empty the read FIFO.
1 Read FIFO is empty.
17.3.5 SPI data register high (SPIx_DH)
Refer to the description of the DL register.
Address: 30A0h base + 4h offset = 30A4h
Bit 7 6 5 4 3 2 1 0
Read
Bits[15:8]
Write
Reset 0 0 0 0 0 0 0 0
SPI1_DH field descriptions
Field Description
Bits[15:8] Data (high byte)
Memory map/register definition
MC9S08PT60 Reference Manual, Rev. 4, 08/2014
482 Freescale Semiconductor, Inc.