Freescale Semiconductor MC9S08PT60, Reference Manual

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the end of the pipe, the CPU executes a BGND instruction to go to active background
mode rather than executing the tagged opcode. A force-type breakpoint causes the CPU
to finish the current instruction and then go to active background mode.
If the background mode has not been enabled (ENBDM = 1) by a serial
WRITE_CONTROL command through the BKGD pin, the CPU will execute an SWI
instruction instead of going to active background mode.
24.4 Memory map and register description
This section contains the descriptions of the BDCand DBG registers and control bits.
Refer to the high-page register summary in the device overview chapter of this data sheet
for the absolute address assignments for all DBG registers. This section refers to registers
and control bits only by their names. A Freescale-provided equate or header file is used to
translate these names into the appropriate absolute addresses.
BDC memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
0 BDC Status and Control Register (BDC_SCR) 8 R/W 00h 24.4.1/643
1 BDC Breakpoint Match Register: High (BDC_BKPTH) 8 R/W 00h 24.4.2/645
2 BDC Breakpoint Register: Low (BDC_BKPTL) 8 R/W 00h 24.4.3/646
3
System Background Debug Force Reset Register
(BDC_SBDFR)
8
W
(always
reads 0)
00h 24.4.4/646
24.4.1 BDC Status and Control Register (BDC_SCR)
This register can be read or written by serial BDC commands (READ_STATUS and
WRITE_CONTROL) but is not accessible to user programs because it is not located in
the normal memory map of the MCU.
NOTE
The reset values shown in the register figure are those in the
normal reset conditions. If the MCU is reset in BDM, ENBDM,
BDMACT, CLKSW will be reset to 1 and others all be to 0.
Chapter 24 Development support
MC9S08PT60 Reference Manual, Rev. 4, 08/2014
Freescale Semiconductor, Inc. 643