Freescale Semiconductor MC9S08PT60, Reference Manual

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SCIx_C3 field descriptions (continued)
Field Description
1
FEIE
Framing Error Interrupt Enable
This bit enables the framing error flag (FE) to generate hardware interrupt requests.
0 FE interrupts disabled; use polling).
1 Hardware interrupt requested when FE is set.
0
PEIE
Parity Error Interrupt Enable
This bit enables the parity error flag (PF) to generate hardware interrupt requests.
0 PF interrupts disabled; use polling).
1 Hardware interrupt requested when PF is set.
15.3.8 SCI Data Register (SCIx_D)
This register is actually two separate registers. Reads return the contents of the read-only
receive data buffer and writes go to the write-only transmit data buffer. Reads and writes
of this register are also involved in the automatic flag clearing mechanisms for the SCI
status flags.
Address: Base a 7h offset
Bit 7 6 5 4 3 2 1 0
Read
R7T7 R6T6 R5T5 R4T4 R3T3 R2T2 R1T1 R0T0
Write
Reset 0 0 0 0 0 0 0 0
SCIx_D field descriptions
Field Description
7
R7T7
Read receive data buffer 7 or write transmit data buffer 7.
6
R6T6
Read receive data buffer 6 or write transmit data buffer 6.
5
R5T5
Read receive data buffer 5 or write transmit data buffer 5.
4
R4T4
Read receive data buffer 4 or write transmit data buffer 4.
3
R3T3
Read receive data buffer 3 or write transmit data buffer 3.
2
R2T2
Read receive data buffer 2 or write transmit data buffer 2.
1
R1T1
Read receive data buffer 1 or write transmit data buffer 1.
0
R0T0
Read receive data buffer 0 or write transmit data buffer 0.
Register definition
MC9S08PT60 Reference Manual, Rev. 4, 08/2014
428 Freescale Semiconductor, Inc.