NVM_FCNFG field descriptions
Field
Description
7
CCIE
Command Complete Interrupt Enable
The CCIE bit controls interrupt generation when a flash command has completed.
0
Command complete interrupt disabled.
1
An interrupt will be requested whenever the CCIF flag in the FSTAT register is set.
6–5
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
4
IGNSF
Ignore Single Bit Fault
The IGNSF controls single bit fault reporting in the FERSTAT register.
0
All single bit faults detected during array reads are reported.
1
Single bit faults detected during array reads are not reported and the single bit fault interrupt will not
be generated.
3–2
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
1
FDFD
Force Double Bit Fault Detect
The FDFD bit allows the user to simulate a double bit fault during flash array read operations and check
the associated interrupt routine. The FDFD bit is cleared by writing a 0 to FDFD.
0
Flash array read operations will set the FERSTAT[DFDIF] flag only if a double bit fault is detected.
1
Any flash array read operation will force the FERSTAT[DFDIF] flag to be set and an interrupt will be
generated as long as the DFDIE interrupt enable in the FERCNFG register is set.
0
FSFD
Force Single Bit Fault Detect
The FSFD bit allows the user to simulate a single bit fault during flash array read operations and check the
associated interrupt routine. The FSFD bit is cleared by writing a 0 to FSFD.
0
Flash array read operations will set the SFDIF flag in the FERSTAT register only if a single bit fault is
detected.
1
Flash array read operation will force the SFDIF flag in the FERSTAT register to be set and an interrupt
will be generated as long as the SFDIE interrupt enable in the FERCNFG register is set.
4.6.5 Flash Error Configuration Register (NVM_FERCNFG)
The FERCNFG register enables the flash error interrupts for the FERSTAT flags.
Address: 3020h base + 5h offset = 3025h
Bit
7
6
5
4
3
2
1
0
Read
Write
Reset
0
0
0
0
0
0
0
0
Flash and EEPROM registers descriptions
MC9S08PT60 Reference Manual, Rev. 4, 08/2014
112
Freescale Semiconductor, Inc.
Summary of Contents for MC9S08PT60
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Page 200: ...Port data registers MC9S08PT60 Reference Manual Rev 4 08 2014 200 Freescale Semiconductor Inc...
Page 396: ...FTM Interrupts MC9S08PT60 Reference Manual Rev 4 08 2014 396 Freescale Semiconductor Inc...
Page 676: ...Resets MC9S08PT60 Reference Manual Rev 4 08 2014 676 Freescale Semiconductor Inc...
