Freescale Semiconductor MC9S08PT60, Reference Manual

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13.6.1 MTIM Status and Control Register (MTIMx_SC)
MTIM_SC contains the overflow status flag and control bits that are used to configure
the interrupt enable, reset the counter, and stop the counter.
Address: Base a 0h offset
Bit 7 6 5 4 3 2 1 0
Read
TOF TOIE
0
TSTP
0
Write TRST
Reset
0 0 0 1 0 0 0 0
MTIMx_SC field descriptions
Field Description
7
TOF
MTIM Overflow Flag
This bit is set when the MTIM counter register overflows to 0x00 after reaching the value in the MTIM
modulo register. Clear TOF by reading the MTIM_SC register while TOF is set, then write a 0 to TOF. TOF
is also cleared when TRST is written to a 1 or when any value is written to the MTIM_MOD register.
0 MTIM counter has not reached the overflow value in the MTIM modulo register.
1 MTIM counter has reached the overflow value in the MTIM modulo register.
6
TOIE
MTIM Overflow Interrupt Enable
This read/write bit enables MTIM overflow interrupts. If TOIE is set, then an interrupt is generated when
TOF = 1. Reset clears TOIE. Do not set TOIE if TOF = 1. Clear TOF first, then set TOIE.
0 TOF interrupts are disabled. Use software polling.
1 TOF interrupts are enabled.
5
TRST
MTIM Counter Reset
When a 1 is written to this write-only bit, the MTIM counter register resets to 0x00 and TOF is cleared.
Reading this bit always returns 0.
0 No effect. MTIM counter remains at current state.
1 MTIM counter is reset to 0x00.
4
TSTP
MTIM Counter Stop
When set, this read/write bit stops the MTIM counter at its current value. Counting resumes from the
current value when TSTP is cleared. Reset sets TSTP to prevent the MTIM from counting.
0 MTIM counter is active.
1 MTIM counter is stopped.
Reserved This field is reserved.
This read-only field is reserved and always has the value 0.
Register definition
MC9S08PT60 Reference Manual, Rev. 4, 08/2014
400 Freescale Semiconductor, Inc.