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Freescale Semiconductor MC9S08PT60, Reference Manual

The Freescale Semiconductor MC9S08PT60 is a powerful microcontroller that offers exceptional performance. To fully utilize its capabilities, make sure to download the Reference Manual for free from manualshive.com. This manual provides detailed instructions on how to maximize the potential of this product.

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IPC_ILRSn field descriptions

Field

Description

7–6

ILRn3

Interrupt Level Register for Source n*4+3

This field sets the interrupt level for interrupt source n*4+3.

5–4

ILRn2

Interrupt Level Register for Source n*4+2

This field sets the interrupt level for interrupt source n*4+2.

3–2

ILRn1

Interrupt Level Register for Source n*4+1

This field sets the interrupt level for interrupt source n*4+1.

ILRn0

Interrupt Level Register for Source n*4+0

This field sets the interrupt level for interrupt source n*4+0.

Interrupt priority control register

MC9S08PT60 Reference Manual, Rev. 4, 08/2014

136

Freescale Semiconductor, Inc.

Summary of Contents for MC9S08PT60

Page 1: ...MC9S08PT60 Reference Manual Supports MC9S08PT60 A and MC9S08PT32 A Document Number MC9S08PT60RM Rev 4 08 2014...

Page 2: ...MC9S08PT60 Reference Manual Rev 4 08 2014 2 Freescale Semiconductor Inc...

Page 3: ...rt A input output I O pins PTA7 PTA0 50 2 2 7 Port B input output I O pins PTB7 PTB0 50 2 2 8 Port C input output I O pins PTC7 PTC0 50 2 2 9 Port D input output I O pins PTD7 PTD0 50 2 2 10 Port E in...

Page 4: ...nd registers 60 3 5 1 System Power Management Status and Control 1 Register PMC_SPMSC1 60 3 5 2 System Power Management Status and Control 2 Register PMC_SPMSC2 62 Chapter 4 Memory map 4 1 Memory map...

Page 5: ...AT 113 4 6 7 Flash Error Status Register NVM_FERSTAT 114 4 6 8 Flash Protection Register NVM_FPROT 115 4 6 9 EEPROM Protection Register NVM_EEPROT 116 4 6 10 Flash Common Command Object Register High...

Page 6: ...135 Chapter 6 System control 6 1 System device identification SDID 137 6 2 Universally unique identification UUID 137 6 3 Reset and system initialization 137 6 4 System options 138 6 4 1 BKGD pin ena...

Page 7: ...dress Register Low SYS_ILLAL 152 6 6 11 Universally Unique Identifier Register 1 SYS_UUID1 152 6 6 12 Universally Unique Identifier Register 2 SYS_UUID2 153 6 6 13 Universally Unique Identifier Regist...

Page 8: ...TDOE 172 7 7 14 Port E Output Enable Register PORT_PTEOE 173 7 7 15 Port F Output Enable Register PORT_PTFOE 174 7 7 16 Port G Output Enable Register PORT_PTGOE 175 7 7 17 Port H Output Enable Registe...

Page 9: ...management 8 1 Clock module 201 8 2 Internal clock source ICS 203 8 2 1 Function description 203 8 2 1 1 Bus frequency divider 204 8 2 1 2 Low power bit usage 204 8 2 1 3 Internal reference clock ICSI...

Page 10: ...clock gating 216 8 6 ICS control registers 216 8 6 1 ICS Control Register 1 ICS_C1 217 8 6 2 ICS Control Register 2 ICS_C2 218 8 6 3 ICS Control Register 3 ICS_C3 219 8 6 4 ICS Control Register 4 ICS...

Page 11: ...n 236 9 8 1 2 FTM1 interconnection 237 9 8 1 3 FTM2 interconnection 237 9 8 2 8 bit modulo timer MTIM 237 9 8 2 1 MTIM0 as ADC hardware trigger 239 9 8 3 Real time counter RTC 239 9 9 Communication in...

Page 12: ...TSI channel assignments 260 9 11 2 2 Hardware trigger 261 Chapter 10 Central processor unit 10 1 Introduction 263 10 1 1 Features 263 10 2 Programmer s Model and CPU Registers 264 10 2 1 Accumulator...

Page 13: ...1 Direct to Direct 272 10 3 7 2 Immediate to Direct 272 10 3 7 3 Indexed to Direct Post Increment 272 10 3 7 4 Direct to Indexed Post Increment 273 10 4 Operation modes 273 10 4 1 Stop mode 273 10 4 2...

Page 14: ...vity 296 11 5 2 Edge and level sensitivity 296 11 5 3 KBI Pullup Resistor 296 11 5 4 KBI initialization 296 Chapter 12 FlexTimer Module FTM 12 1 Introduction 299 12 1 1 FlexTimer philosophy 299 12 1 2...

Page 15: ...6 Initial State for Channel Output FTMx_OUTINIT 322 12 3 17 Output Mask FTMx_OUTMASK 324 12 3 18 Function for Linked Channels FTMx_COMBINEn 325 12 3 19 Deadtime Insertion Control FTMx_DEADTIME 327 12...

Page 16: ...ers 358 12 4 10 3 CnVH L registers 359 12 4 11 PWM synchronization 360 12 4 11 1 Hardware trigger 360 12 4 11 2 Software trigger 361 12 4 11 3 Boundary cycle 362 12 4 11 4 MODH L registers synchroniza...

Page 17: ...rement 388 12 4 21 5 Read coherency mechanism 390 12 4 22 TPM emulation 392 12 4 22 1 MODH L and CnVH L synchronization 392 12 4 22 2 Free running counter 392 12 4 22 3 Write to SC 392 12 4 22 4 Write...

Page 18: ...Real time counter RTC 14 1 Introduction 405 14 2 Features 405 14 2 1 Modes of operation 405 14 2 1 1 Wait mode 405 14 2 1 2 Stop modes 406 14 2 2 Block diagram 406 14 3 External signal description 40...

Page 19: ...ontrol Register 2 SCIx_C2 422 15 3 5 SCI Status Register 1 SCIx_S1 423 15 3 6 SCI Status Register 2 SCIx_S2 425 15 3 7 SCI Control Register 3 SCIx_C3 427 15 3 8 SCI Data Register SCIx_D 428 15 4 Funct...

Page 20: ...2 External Signal Description 444 16 2 1 SPSCK SPI Serial Clock 445 16 2 2 MOSI Master Data Out Slave Data In 445 16 2 3 MISO Master Data In Slave Data Out 445 16 2 4 SS Slave Select 445 16 3 Register...

Page 21: ...in Stop Mode 463 16 4 9 Reset 463 16 4 10 Interrupts 464 16 4 10 1 MODF 464 16 4 10 2 SPRF 464 16 4 10 3 SPTEF 465 16 4 10 4 SPMF 465 16 5 Initialization Application Information 465 16 5 1 Initializat...

Page 22: ...3 6 SPI Data Register low SPIx_DL 483 17 3 7 SPI match register high SPIx_MH 484 17 3 8 SPI Match Register low SPIx_ML 484 17 3 9 SPI control register 3 SPIx_C3 485 17 3 10 SPI clear interrupt regist...

Page 23: ...ation sequence 503 17 5 2 Pseudo Code Example 503 Chapter 18 Inter Integrated Circuit I2C 18 1 Introduction 507 18 1 1 Features 507 18 1 2 Modes of operation 508 18 1 3 Block diagram 508 18 2 I2C sign...

Page 24: ...522 18 4 1 4 STOP signal 522 18 4 1 5 Repeated START signal 523 18 4 1 6 Arbitration procedure 523 18 4 1 7 Clock synchronization 523 18 4 1 8 Handshaking 524 18 4 1 9 Clock stretching 524 18 4 1 10 I...

Page 25: ...Voltage Reference High VREFH 539 19 2 4 Voltage Reference Low VREFL 539 19 2 5 Analog Channel Inputs ADx 539 19 3 ADC Control Registers 540 19 3 1 Status and Control Register 1 ADC_SC1 540 19 3 2 Stat...

Page 26: ...operation 559 19 4 8 MCU Stop3 mode operation 560 19 4 8 1 Stop3 mode with ADACK disabled 560 19 4 8 2 Stop3 mode with ADACK enabled 560 19 5 Initialization information 561 19 5 1 ADC module initializ...

Page 27: ...20 1 2 3 Operation in Debug mode 572 20 1 3 Block diagram 572 20 2 External signal description 573 20 3 Memory map and register definition 573 20 3 1 ACMP Control and Status Register ACMP_CS 574 20 3...

Page 28: ...TSI Counter Register High TSI_CNTH 589 21 3 8 TSI Counter Register Low TSI_CNTL 589 21 4 Functional description 590 21 4 1 Capacitance measurement 590 21 4 1 1 TSI electrode oscillator 590 21 4 1 2 E...

Page 29: ...egister CRC_P1 608 22 5 7 CRC Polynomial 2 Register CRC_P2 608 22 5 8 CRC Polynomial 3 Register CRC_P3 609 22 5 9 CRC Control Register CRC_CTRL 609 22 6 Functional description 610 22 6 1 16 bit CRC ca...

Page 30: ...2 23 3 1 2 Refreshing the Watchdog 622 23 3 1 3 Example code Refreshing the Watchdog 623 23 3 2 Configuring the Watchdog 623 23 3 2 1 Reconfiguring the Watchdog 623 23 3 2 2 Unlocking the Watchdog 624...

Page 31: ...n 643 24 4 1 BDC Status and Control Register BDC_SCR 643 24 4 2 BDC Breakpoint Match Register High BDC_BKPTH 645 24 4 3 BDC Breakpoint Register Low BDC_BKPTL 646 24 4 4 System Background Debug Force R...

Page 32: ...T 662 25 3 15 Debug Status Register DBG_S 664 25 3 16 Debug Count Status Register DBG_CNT 665 25 4 Functional description 666 25 4 1 Comparator 666 25 4 1 1 RWA and RWAEN in full modes 666 25 4 1 2 Co...

Page 33: ...Section number Title Page 25 5 Resets 675 MC9S08PT60 Reference Manual Rev 4 08 2014 Freescale Semiconductor Inc 33...

Page 34: ...MC9S08PT60 Reference Manual Rev 4 08 2014 34 Freescale Semiconductor Inc...

Page 35: ...al availability per package type for the devices available Table 1 1 Memory and package availability Feature MC9S08PT60 MC9S08PT32 Flash size bytes 60 864 32 768 EEPROM size bytes 256 256 RAM size byt...

Page 36: ...MTIM0 Yes MTIM1 Yes SPI0 8 bit Yes SPI1 16 bit Yes IIC Yes ACMP Yes SCI0 Yes SCI1 Yes SCI2 Yes No ADC channels 16 12 12 12 TSI channels 16 12 12 12 KBI pins 16 16 12 12 GPIO 57 41 37 28 1 2 MCU block...

Page 37: ...TxD2 PTE1 MOSI0 PTE2 MISO0 PTE3 SS0 PTE4 PTE5 PTE6 PTE7 TCLK2 PTF0 TSI12 PTF1 TSI13 PTF2 TSI14 PTF3 TSI15 PTF4 ADP12 PTF5 ADP13 PTF6 ADP14 PTF7 ADP15 PTG0 PTG1 PTG2 PTG3 PTH0 FTM2CH0 PTH1 FTM2CH1 PTH2...

Page 38: ...ower oscillator providing 1 kHz reference clock to RTC and watchdog WDOG NOTE For this device the system clock is the bus clock The following figure shows a simplified clock connection diagram ICSLCLK...

Page 39: ...selected as clock source to the FTM and MTIM modules The frequency of the ICSFFCLK is determined by the setting of the ICS LPOCLK This clock is generated from an internal low power oscillator 1 kHz th...

Page 40: ...System clock distribution MC9S08PT60 Reference Manual Rev 4 08 2014 40 Freescale Semiconductor Inc...

Page 41: ...Chapter 2 Pins and connections 2 1 Device pin assignment MC9S08PT60 Reference Manual Rev 4 08 2014 Freescale Semiconductor Inc 41...

Page 42: ...H0 RTCO PTA5 IRQ TCLK0 RESET PTA4 ACMPO BKGD MS PTD1 KBI1P1 FTM2CH3 MOSI11 PTD0 KBI1P0 FTM2CH2 SPSCK11 PTH7 PTH6 PTE7 TCLK2 PTH2 BUSOUT VDD VDDA VREFH VSSA VREFL VSS VSS PTB7 SCL EXTAL PTB6 SDA XTAL P...

Page 43: ...IRQ TCLK0 RESET PTA4 ACMPO BKGD MS PTD1 KBI1P1 FTM2CH3 MOSI11 PTD0 KBI1P0 FTM2CH2 SPSCK11 PTE7 TCLK2 PTH2 BUSOUT VDD VDDA VREFH VSSA VREFL VSS VSS PTB7 SCL EXTAL PTB6 SDA XTAL PTE5 PTB5 FTM2CH5 SS0 1...

Page 44: ...TA4 ACMPO BKGD MS PTD1 KBI1P1 FTM2CH3 MOSI11 PTD0 KBI1P0 FTM2CH2 SPSCK11 PTE7 TCLK2 PTH2 BUSOUT VDD VDDA VREFH VSSA VREFL VSS VSS PTB7 SCL EXTAL PTB6 SDA XTAL PTB5 FTM2CH5 SS0 1 PTB4 FTM2CH4 MISO0 1 P...

Page 45: ...TAL PTB6 SDA XTAL PTB5 FTM2CH5 SS0 1 PTB4 FTM2CH4 MISO0 1 PTC2 FTM2CH2 ADP10 PTC1 FTM2CH1 ADP9 TSI7 PTC0 FTM2CH0 ADP8 TSI6 1 High source sink current pins 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31...

Page 46: ...the power supply pins for the analog to digital converter ADC Connect the VDDA pin to the same voltage potential as VDD and the VSSA pin to the same voltage potential as VSS De coupling of these pins...

Page 47: ...crystal or resonator circuit RF is used to provide a bias path to keep the EXTAL input in its linear range during crystal startup its value is not generally critical Typical systems use 1 M to 10 M H...

Page 48: ...manual external reset can be added by supplying a simple switch to ground pull reset pin low to force a reset When the RESET pin function is enabled an internal pullup resistor is connected to this p...

Page 49: ...U into active background mode The BKGD pin is used primarily for background debug controller BDC communications using a custom protocol that uses 16 clock cycles of the target MCU s BDC clock per bit...

Page 50: ...devices when configured for input mode the pullup devices are selectable on an individual port bit basis The pulling devices are disengaged when configured for output mode 2 2 8 Port C input output I...

Page 51: ...ort pins These port pins also have selectable pull up devices when configured for input mode the pullup devices are selectable on an individual port bit basis The pulling devices are disengaged when c...

Page 52: ...is configured as general purpose input or when a peripheral uses the port pin as an input the software can enable a pullup device When a high current drive port pin is configured as general purpose ou...

Page 53: ...11 21 17 15 12 PTC2 FTM2CH2 ADP10 22 18 16 PTD7 KBI1P7 TXD2 23 19 17 PTD6 KBI1P6 RXD2 24 20 18 PTD5 KBI1P5 25 21 19 13 PTC1 FTM2CH1 ADP9 TSI7 26 22 20 14 PTC0 FTM2CH0 ADP8 TSI6 27 PTF7 ADP15 28 PTF6 A...

Page 54: ...FTM1CH0 RTCO 63 47 43 31 PTA5 IRQ TCLK0 RESET 64 48 44 32 PTA4 ACMPO BKGD MS 1 This is a high current drive pin when operated as output Please see High current drive for more information 2 This is a t...

Page 55: ...s clocks are running Full voltage regulation is maintained Stop3 modes System clocks stopped voltage regulator in standby all internal circuits powered for fast recovery 3 2 1 Run mode This is the nor...

Page 56: ...e clocks in the MCU are halted by default but OSC clock and internal reference clock can be turned on by setting the ICS control registers The ICS enters its standby state as does the voltage regulato...

Page 57: ...e 3 2 5 LVD enabled in stop mode The LVD system is capable of generating either an interrupt or a reset when the supply voltage drops below the LVD voltage If the LVD is enabled in stop LVDE and LVDSE...

Page 58: ...nditions in order to protect memory contents and control MCU system states during supply voltage variations This system consists of a power on reset POR circuit and an LVD circuit with a user selectab...

Page 59: ...y setting SPMSC1 LVDRE to 1 After an LVD reset has occurred the LVD system will hold the MCU in reset until the supply voltage has risen above the level determined by LVDV The SRS LVD bit is set follo...

Page 60: ...00h 3 5 2 62 3 5 1 System Power Management Status and Control 1 Register PMC_SPMSC1 This high page register contains status and control bits to support the low voltage detection function and to enabl...

Page 61: ...ter reset Additional writes are ignored 0 LVD events do not generate hardware resets 1 Force an MCU reset when an enabled low voltage detect event occurs 3 LVDSE Low Voltage Detect Stop Enable Provide...

Page 62: ...field is reserved and always has the value 0 6 LVDV Low Voltage Detect Voltage Select This write once bit selects the low voltage detect LVD trip point setting See data sheet for details 0 Low trip p...

Page 63: ...08PT32 32 768 bytes 64 pages of 512 bytes each Random access memory RAM MC9S08PT60 4 096 bytes MC9S08PT32 4 096 bytes Electrically erasable programmable read only memory EEPROM MC9S08PT60 256 bytes 12...

Page 64: ...ry map 4 2 Reset and interrupt vector assignments The following table shows address assignments for reset and interrupt vectors The vector names shown in this table are the labels used in the Freescal...

Page 65: ...l 1 Vftm1ch1 0xFFE4 FFE5 FTM1 channel 0 Vftm1ch0 0xFFE6 FFE7 FTM2 overflow Vftm2ovf 0xFFE8 FFE9 FTM2 channel 5 Vftm2ch5 0xFFEA FFEB FTM2 channel 4 Vftm2ch4 0xFFEC FFED FTM2 channel 3 Vftm2ch3 0xFFEE F...

Page 66: ...DOG 0x3038 0x303E 7 ICS XOSC 0x3040 0x3041 2 PMC 0x304A 0x304B 2 SYS 0x3050 0x3059 10 IPC 0x3060 0x3068 9 CRC 0x306A 0x306F 6 RTC 0x3070 0x307B 12 IIC 0x307C 0x307D 2 KBI0 0x307E 0x307F 2 KBI1 0x3080...

Page 67: ...te unused or reserved bit locations that could read as 1s or 0s Table 4 3 Direct page register allocation Address Register name Bit 7 6 5 4 3 2 1 Bit 0 0x0000 PORT_PTAD PTAD7 PTAD6 PTAD5 PTAD4 PTAD3 P...

Page 68: ...CHIE MSB MSA ELSB ELSA 0x0026 FTM0_C0VH Bit 15 14 13 12 11 10 9 Bit 8 0x0027 FTM0_C0VL Bit 7 6 5 4 3 2 1 Bit 0 0x0028 FTM0_C1SC CHF CHIE MSB MSA ELSB ELSA 0x0029 FTM0_C1VH Bit 15 14 13 12 11 10 9 Bit...

Page 69: ...3005 SYS_SOPT2 TXDME FTMSY NC RXDFE RXDCE ACIC RTCC ADHWTS 0x3006 SYS_SOPT3 DLYACT CLKOE BUSREF 0x3007 SYS_SOPT4 DELAY 0x3008 0x300B Reserved 0x300C SCG_C1 FTM2 FTM1 FTM0 MTIM1 MTIM0 RTC 0x300D SCG_C2...

Page 70: ...1 0 CCOB9 CCOB8 0x302B NVM_FCCOBLO CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0 0x302C NVM_FOPT NV7 NV6 NV5 NV4 NV3 NV2 NV1 NV0 0x302D 0x302F Reserved 0x3030 WDOG_CS1 EN INT UPDAT E TST DBG WAIT ST...

Page 71: ...ILRS9 ILR39 ILR38 ILR37 ILR36 0x305A 0x305F Reserved 0x3060 CRC_D0 Bit 31 30 29 28 27 26 25 Bit 24 0x3061 CRC_D1 Bit 23 22 21 20 19 18 17 Bit 16 0x3062 CRC_D2 Bit 15 14 13 12 11 10 9 Bit 8 0x3063 CRC_...

Page 72: ...PS SCISWA I RSRC M WAKE ILT PE PT 0x3083 SCI0_C2 TIE TCIE RIE ILIE TE RE RWU SBK 0x3084 SCI0_S1 TDRE TC RDRF IDLE OR NF FE PF 0x3085 SCI0_S2 LBKDIF RXEDGI F RXINV RWUID BRK13 LBKDE RAF 0x3086 SCI0_C3...

Page 73: ...0 0x30A6 SPI1_MH Bit 15 14 13 12 11 10 9 Bit 8 0x30A7 SPI1_ML Bit 7 6 5 4 3 2 1 Bit 0 0x30A8 SPI1_C3 TNEAR EF_MA RK RNFULL F_MAR K INTCLR TNEARI EN RNFULL IEN FIFOMO DE 0x30A9 SPI1_CI TXFER R RXFER R...

Page 74: ...Bit 0 0x30C5 FTM2_C0SC CHF CHIE MSB MSA ELSB ELSA 0x30C6 FTM2_C0VH Bit 15 14 13 12 11 10 9 Bit 8 0x30C7 FTM2_C0VL Bit 7 6 5 4 3 2 1 Bit 0 0x30C8 FTM2_C1SC CHF CHIE MSB MSA ELSB ELSA 0x30C9 FTM2_C1VH...

Page 75: ...ULT2 EN FAULT1 EN FAULT0 EN 0x30EA 0x30EB Reserved 0x30EC PORT_IOFLT0 FLTD FLTC FLTB FLTA 0x30ED PORT_IOFLT1 FLTH FLTG FLTF FLTE 0x30EE PORT_IOFLT2 FLTKBI1 FLTKBI0 FLTRST 0x30EF PORT_FCLKDIV FLTDIV3 F...

Page 76: ...0xFF71 NV_BACKKEY1 BACKKEY1 0xFF72 NV_BACKKEY2 BACKKEY2 0xFF73 NV_BACKKEY3 BACKKEY3 0xFF74 NV_BACKKEY4 BACKKEY4 0xFF75 NV_BACKKEY5 BACKKEY5 0xFF76 NV_BACKKEY6 BACKKEY6 0xFF77 NV_BACKKEY7 BACKKEY7 0xFF...

Page 77: ...sed RAM variables and bit addressable program variables Include the following 2 instruction sequence in your reset initialization routine where RamLast is equated to the highest address of the RAM in...

Page 78: ...le a command erase program is executing on flash memory Simultaneous EEPROM memory are implemented with error correction codes ECC that can resolve single bit faults and detect double bit faults The f...

Page 79: ...ash memory program and erase operations Interrupt generation on flash command completion and flash error detection Security mechanism to prevent unauthorized access to the flash memory 4 5 2 Function...

Page 80: ...initialization after system reset On each system reset the flash and EEPROM module executes an initialization sequence that establishes initial values for the flash and EEPROM block configuration par...

Page 81: ...OM program and erase command operations 2 Use command write sequence to set flash and EEPROM command parameters and launch execution 3 Execute valid flash and EEPROM commands according to MCU function...

Page 82: ...er to launch command Read FSTAT register CCIF Set Bit Polling for Command Completion Check Clear CCIF 0x80 Parameters Write FSTAT register Clear ACCERR FPVIOL 0x30 or FPVIOL Set Access Error and Prote...

Page 83: ...7 6 8 6 0x07 8 6 9 6 0x08 9 6 10 6 0x09 10 6 11 6 0x0A 11 6 12 6 0x0B 12 6 13 6 0x0C 13 6 14 6 0x0D 14 6 15 6 0x0E 15 6 16 6 0x0F 16 6 17 6 0x10 17 6 18 6 0x11 18 6 19 6 0x12 19 6 20 0 0x13 1 BUSCLK i...

Page 84: ...to provide a command code and its relevant parameters to the memory controller First the user must set up all required FCCOB field Then they can initiate the command s execution by writing a 1 to the...

Page 85: ...memory controller will return FSTAT CCIF to 1 and the FCCOB register will be used to communicate any results The following table presents the valid flash and EEPROM commands as enabled by the combinat...

Page 86: ...CCIF FSTAT register CCIE FCNFG register I Bit ECC double bit fault on flash and EEPROM read DFDIF FERSTAT register DFDIE FERCNFG register I Bit ECC single bit fault on flash and EEPROM read SFDIF FER...

Page 87: ...be activated for protection The flash memory addresses covered by these protectable regions are shown in the flash memory map The higher address region is mainly targeted to hold the boot loader code...

Page 88: ...EPROM module provides protection to the MCU During the reset sequence the FPROT register is loaded with the contents of the flash protection byte in the flash configuration field at global address 0xF...

Page 89: ...Flash Start Address 0x8000 0xFFFF FPOPEN 0 FPOPEN 0 FPOPEN 0 FPOPEN 0 FPOPEN 0 Figure 4 6 Flash protection scenarios The general guideline is that flash protection can only be added and not removed T...

Page 90: ...al address range Protected size 00 0x8000 0x83FF 1 Kbytes 01 0x8000 0x87FF 2 Kbytes 10 0x8000 0x8FFF 4 Kbytes 11 0x8000 0x9FFF 8 Kbytes During the reset sequence fields NVM_EEPROT DPOPEN and NVM_EEPRO...

Page 91: ...nd EEPROM erase and program commands are available and that the upper region of the flash is unprotected If the flash security byte is successfully programmed its new value will take affect after the...

Page 92: ...mmand A reset of the MCU is the only method to re enable the verify backdoor access key command The security as defined in the flash and EEPROM security byte 0xFF7F is not changed by using the verify...

Page 93: ...flash block and other resources within the flash and EEPROM module Table 4 17 Flash commands FCMD Command Function on flash memory 0x01 Erase verify all blocks Verify that all flash and EEPROM blocks...

Page 94: ...ocks are erased 0x02 Erase verify block Verify that an EEPROM block is erased 0x08 Erase all block Erase all EEPROM and flash blocks An erase of all EEPROM blocks is possible only when the FPROT FPLDI...

Page 95: ...EEPROM command summary This section provides details of all available flash commands launched by a command write sequence The FSTAT ACCERR bit will be set during the command write sequence if any of...

Page 96: ...both NVM_FSTAT MGSTAT bits will be set Table 4 21 Erase verify all blocks command error handling Register Error bit Error condition NVM_FSTAT ACCERR Set if CCOBIX 2 0 000 at command launch FPVIOL None...

Page 97: ...sh section command The erase verify flash section command will verify that a section of code in the flash memory is erased The erase verify flash section command defines the starting point of the code...

Page 98: ...and can not be erased It can be used to store the product ID or any other information that can be written only once It is programmed using the program once command described in Program once command To...

Page 99: ...eters 000 0x06 Global address 23 16 to identify flash block 001 Global address 15 0 of longwords location to be programmed1 010 Word 0 longword 0 program value 011 Word 1 longword 0 program value 100...

Page 100: ...mmand must not be executed from the flash block containing the program once reserved field Table 4 30 Program once command FCCOB requirements CCOBIX 2 0 FCCOB parameters 000 0x07 Not required 001 Prog...

Page 101: ...red Upon clearing NVM_FSTAT CCIF to launch the erase all blocks command the memory controller will erase the entire NVM memory space and verify that it is erased If the memory controller verifies that...

Page 102: ...able 4 9 Set if an invalid global address 23 16 is supplied1 FPVIOL Set if an area of the selected flash block is protected MGSTAT1 Set if any errors have been encountered during the verify operation2...

Page 103: ...nd the memory controller will erase the entire flash and EEPROM memory space and verify that it is erased If the memory controller verifies that the entire flash and EEPROM memory space was properly e...

Page 104: ...controller sets the NVM_FSTAT ACCERR bit If the command is enabled the memory controller compares the key provided in FCCOB to the backdoor comparison key in the flash configuration field with Key 0 c...

Page 105: ...e eventually share the same address on the MCU global memory map Upon clearing NVM_FSTAT CCIF to launch the set user margin level command the memory controller will set the user margin level for the t...

Page 106: ...t of the data to be verified and the number of bytes Table 4 45 Erase verify EEPROM section command FCCOB requirements CCOBIX 2 0 NVM_FCCOBHI parameters NVM_FCCOBLO parameters 000 0x10 Global address...

Page 107: ...Program EEPROM command FCCOB requirements CCOBIX 2 0 NVM_FCCOBHI parameters NVM_FCCOBLO parameters 000 0x11 Global address 23 16 to identify the EEPROM block 001 Global address 15 0 of the first word...

Page 108: ...ess 23 16 to identify EEPROM block 001 Global address 15 0 anywhere within the sector to be erased See Overview for EEPROM sector size Upon clearing NVM_FSTAT CCIF to launch the erase EEPROM sector co...

Page 109: ...6 4 111 3025 Flash Error Configuration Register NVM_FERCNFG 8 R W 00h 4 6 5 112 3026 Flash Status Register NVM_FSTAT 8 R W 80h 4 6 6 113 3027 Flash Error Status Register NVM_FERSTAT 8 R W 00h 4 6 7 11...

Page 110: ...The FSEC register holds all bits associated with the security of the MCU and NVM module All bits in the FSEC register are readable but not writable During the reset sequence the FSEC register is load...

Page 111: ...2h Bit 7 6 5 4 3 2 1 0 Read 0 CCOBIX Write Reset 0 0 0 0 0 0 0 0 NVM_FCCOBIX field descriptions Field Description 7 3 Reserved This field is reserved This read only field is reserved and always has th...

Page 112: ...ing a 0 to FDFD 0 Flash array read operations will set the FERSTAT DFDIF flag only if a double bit fault is detected 1 Any flash array read operation will force the FERSTAT DFDIF flag to be set and an...

Page 113: ...026h Bit 7 6 5 4 3 2 1 0 Read CCIF 0 ACCERR FPVIOL MGBUSY 0 MGSTAT Write Reset 1 0 0 0 0 0 0 0 NVM_FSTAT field descriptions Field Description 7 CCIF Command Complete Interrupt Flag The CCIF flag indic...

Page 114: ...ntroller Command Completion Status Flag One or more MGSTAT flag bits are set if an error is detected during execution of a flash command or during the flash reset sequence NOTE Reset value can deviate...

Page 115: ...operation returning invalid data was attempted on a flash block that was under a flash command operation The SFDIF flag is cleared by writing a 1 to SFDIF Writing a 0 to SFDIF has no effect on SRFDIF...

Page 116: ...of the flash memory ending with global address 0xFFFF 0 Protection Unprotection enabled 1 Protection Unprotection disabled 4 3 FPHS Flash Protection Higher Address Size The FPHS bits determine the siz...

Page 117: ...med Trying to alter data in any protected area in the EEPROM memory will result in a protection violation error and the FPVIOL bit will be set in the FSTAT register Block erase of the EEPROM memory is...

Page 118: ...ressed via the CCOBIX index found in the FCCOBIX register Byte wide reads and writes are allowed to the FCCOB register Address 3020h base Bh offset 302Bh Bit 7 6 5 4 3 2 1 0 Read CCOB Write Reset 0 0...

Page 119: ...eld Description NV Nonvolatile Bits The NV 7 0 bits are available as nonvolatile bits During the reset sequence the FOPT register is loaded from the flash nonvolatile byte in the flash configuration f...

Page 120: ...Flash and EEPROM registers descriptions MC9S08PT60 Reference Manual Rev 4 08 2014 120 Freescale Semiconductor Inc...

Page 121: ...nitializes the stack pointer and performs other system setups before clearing the I bit to allow the CPU to respond to interrupts When the CPU receives a qualified interrupt request it completes the c...

Page 122: ...ice routine ISR and restore it immediately before the RTI that is used to return from the ISR When two or more interrupts are pending when the I bit is cleared the highest priority source is serviced...

Page 123: ...l be registered so that it can be serviced after completion of the current ISR 5 1 2 Interrupt vectors sources and local masks The following table provides a summary of all interrupt sources High prio...

Page 124: ...fault SPI1 transmit SPI1 match 32 0xFFBE FFBF Vspi0 SPI0 SPRF MODF SPTEF SPMF SPIE SPIE SPTIE SPMIE SPI0 receive SPI0 mode fault SPI0 transmit SPI0 match 31 0xFFC0 FFC1 Vsci2tx SCI2 TRDE TC TIE TCIE...

Page 125: ...FTM1CH1 CH1F CH1IE FTM1 channel 1 13 0xFFE4 FFE5 Vftm1ch0 FTM1CH0 CH0F CH0IE FTM1 channel 0 12 0xFFE6 FFE7 Vftm2ovf FTM2 TOF TOIE FTM2 overflow 11 0xFFE8 FFE9 Vftm2ch5 FTM2CH5 CH5F CH5IE FTM2 channel...

Page 126: ...e Support for prioritized preemptive interrupt service routines Low priority interrupt requests are blocked when high priority interrupt service routines are being serviced Higher or equal priority le...

Page 127: ...0 1 0 Stop Figure 5 2 Interrupt priority controller block diagram The IPC works with the existing HCS08 interrupt mechanism to allow nested interrupts with programmable priority levels This module als...

Page 128: ...upt priority arbitration as defined by the HCS08 CPU because the IPC is an external module Therefore if two or more interrupts are present in the HCS08 CPU at the same time the inherent priority in HC...

Page 129: ...l part which it cannot be interrupted CLI global interrupt enable and nested interrupt enabled continue the less critical BSET PULIPM PULIPM_R restore the old IPM value before leaving RTI then you can...

Page 130: ...IRQF TO CPU FOR INSTRUCTIONS RESET BYPASS STOP STOP BUSCLK IRQPE IRQ 1 0 S IRQEDG SYNCHRO SYNCHRO NIZER NIZER IRQPDD WAKE UP INPUTS MODULES TO INTERNAL IRQACK BIL BIH To pullup enable logic for IRQ F...

Page 131: ...nternal gates connected to this pin are pulled all the way to VDD When enabling the IRQ pin for use the IRQF will be set and must be cleared prior to enabling the interrupt When configuring the pin fo...

Page 132: ...he IRQMOD control bit determines whether the IRQ pin is sensitive to both edges and levels or only edges When the IRQ pin is enabled as the IRQ input and is configured to detect rising edges the optio...

Page 133: ...nterrupt Priority Mask Pseudo Stack Register IPC_IPMPS 8 R 00h 5 4 2 135 3050 Interrupt Level Setting Registers n IPC_ILRS0 8 R W 00h 5 4 3 135 3051 Interrupt Level Setting Registers n IPC_ILRS1 8 R W...

Page 134: ...egister is full It is automatically updated after each IPMPS register push or pull operation If additional interrupt is nested after this bit is set the earliest interrupt mask value IPM0 1 0 stacked...

Page 135: ...tored in IPM3 5 4 IPM2 Interrupt Priority Mask pseudo stack position 2 This field is the pseudo stack register for IPM2 The most recent information is stored in IPM2 3 2 IPM1 Interrupt Priority Mask p...

Page 136: ...e n 4 2 This field sets the interrupt level for interrupt source n 4 2 3 2 ILRn1 Interrupt Level Register for Source n 4 1 This field sets the interrupt level for interrupt source n 4 1 ILRn0 Interrup...

Page 137: ...itions During reset most control and status registers are forced to initial values and the program counter is loaded from the reset vector 0xFFFE 0xFFFF On chip peripheral modules are disabled and I O...

Page 138: ...nable After POR PTA4 ACMPO BKGD MS pin functions as BKGD output The SYS_SOPT1 BKGDPE bit must be set to enable the background debug mode pin enable function When this bit is clear this pin can functio...

Page 139: ...and PTB7 act as IIC pins the remote IIC level is limited to no more than MCU VDD 6 4 6 FTM2 channels pin reassignment After POR reset FTM2 channel pinouts of FTM2CH0 FTM2CH1 FTM2CH2 and FTM2CH3 are de...

Page 140: ...1 ch0 TSI trg 00 01 10 11 ovf TSI_CS0 STM 0 1 ovf PTA6 FTM2FAULT1 ADP2 TSI0 PTA7 FTM2FAULT2 ADP3 TSI1 PTB0 KBI0P4 RxD0 ADP4 TSI2 1 TSI_CS0 SWTS Figure 6 1 System interconnection diagram 6 5 1 ACMP out...

Page 141: ...to other shared functions When this bit is clear the RxD0 pin is connected to SCI0 only SCI0 RXDCE RxD0 RxD0 FTM0 CH1 Figure 6 3 RxD0 capture function diagram 6 5 4 SCI0 RxD filter When SYS_SOPT2 RXD...

Page 142: ...r by writing 1 to the SYS_SOPT2 FTMSYNC bit Writing 0 to this bit takes no effect This bit is always read 0 6 5 7 ADC hardware trigger ADC module may initiate a conversion via a hardware trigger MTIM0...

Page 143: ...legal Address Register High SYS_ILLAH 8 R Undefined 6 6 9 151 304B Illegal Address Register Low SYS_ILLAL 8 R Undefined 6 6 10 152 30F8 Universally Unique Identifier Register 1 SYS_UUID1 8 R Undefined...

Page 144: ...This bit POR to 1 LVR to uncertain value and reset to 0 at any other conditions 0 Reset not caused by POR 1 POR caused reset 6 PIN External Reset Pin Reset was caused by an active low level on the ex...

Page 145: ...t caused by LVD trip or POR 1 Reset caused by LVD trip or POR 0 Reserved This field is reserved This read only field is reserved and always has the value 0 6 6 2 System Background Debug Force Reset Re...

Page 146: ...0h base 2h offset 3002h Bit 7 6 5 4 3 2 1 0 Read Reserved ID Write Reset 0 0 0 0 0 0 0 0 SYS_SDIDH field descriptions Field Description 7 4 Reserved This field is reserved ID Part Identification Numbe...

Page 147: ...e mapped on PTB2 PTB3 PTB4 and PTB5 1 SPI0 SPSCK0 MOSI0 MISO0 and SS0 are mapped on PTE0 PTE1 PTE2 and PTE3 5 IICPS IIC Port Pin Select This write once bit selects the IIC port pins 0 IIC SCL and SDA...

Page 148: ...ion or the MCU may stuck at stop3 mode and cannot wake up by interrupts 0 CPU wakes up as normal 1 CPU wakes up without any interrupt subroutine serviced 0 STOPE Stop Mode Enable This write once bit d...

Page 149: ...t signal is connected to SCI0 module only 1 RXD0 input signal is connected to SCI0 module and FTM0 channel 1 3 ACIC Analog Comparator to Input Capture Enable This bit connects the output of ACMP to FT...

Page 150: ...4 Reserved This field is reserved This read only field is reserved and always has the value 0 3 CLKOE CLK Output Enable This bit enables reference clock output on PTH2 0 ICSCLK output disabled on PTH...

Page 151: ...lo value that is defined 6 6 9 Illegal Address Register High SYS_ILLAH The SYS_ILLAH is a read only register containing the high 8 bit of the illegal address of ILAD reset Address 3000h base 4Ah offse...

Page 152: ...ets to the low 8 bit of the illegal address in other cases the reset to values are undetermined 6 6 11 Universally Unique Identifier Register 1 SYS_UUID1 The read only SYS_UUIDx registers contain a se...

Page 153: ...Description ID 55 48 Universally Unique Identifier 6 6 13 Universally Unique Identifier Register 3 SYS_UUID3 The read only SYS_UUIDx registers contain a series of 63 bit number to identify the unique...

Page 154: ...Description ID 39 32 Universally Unique Identifier 6 6 15 Universally Unique Identifier Register 5 SYS_UUID5 The read only SYS_UUIDx registers contain a series of 64 bit number to identify the unique...

Page 155: ...Description ID 23 16 Universally Unique Identifier 6 6 17 Universally Unique Identifier Register 7 SYS_UUID7 The read only SYS_UUIDx registers contain a series of 64 bit number to identify the unique...

Page 156: ...the unique device in the family Address 3000h base FFh offset 30FFh Bit 7 6 5 4 3 2 1 0 Read ID 7 0 Write Reset x x x x x x x x Notes x Undefined at reset SYS_UUID8 field descriptions Field Descriptio...

Page 157: ...ctions are disabled After reset the shared peripheral functions are disabled so that the pins are controlled by the parallel I O except PTA4 and PTA5 that are default to BKGD MS and RESET function All...

Page 158: ...PTxDn CPU read PTxDn Figure 7 1 Normal I O structure 1 0 PTxPEn PTxOEn PTxIEn PTxDn CPU read PTxDn Figure 7 2 SDA PTA2 SCL PTA3 structure Introduction MC9S08PT60 Reference Manual Rev 4 08 2014 158 Fre...

Page 159: ...ble bit When PTxIEn 1 a read from PTxDn returns the input value of the associated pin when PTxIEn 0 a read from PTxDn returns the last value written to the port data register NOTE The PTxOE must be cl...

Page 160: ...e of the corresponding pullup enable register bit The internal pullup device is also disabled if the pin is controlled by an analog function NOTE When configuring IIC to use SDA PTA2 and SCL PTA3 pins...

Page 161: ...BD 8 R W 00h 7 7 2 163 2 Port C Data Register PORT_PTCD 8 R W 00h 7 7 3 163 3 Port D Data Register PORT_PTDD 8 R W 00h 7 7 4 164 4 Port E Data Register PORT_PTED 8 R W 00h 7 7 5 164 5 Port F Data Regi...

Page 162: ...able Register PORT_PTBPE 8 R W 00h 7 7 31 191 30F2 Port C Pullup Enable Register PORT_PTCPE 8 R W 00h 7 7 32 192 30F3 Port D Pullup Enable Register PORT_PTDPE 8 R W 00h 7 7 33 194 30F4 Port E Pullup E...

Page 163: ...gured as outputs the logic level is driven out of the corresponding MCU pin Reset forces PTBD to all 0s but these 0s are not driven out of the corresponding pins because reset also configures all port...

Page 164: ...configured as outputs the logic level is driven out of the corresponding MCU pin Reset forces PTDD to all 0s but these 0s are not driven out of the corresponding pins because reset also configures al...

Page 165: ...ts of this register For port F pins that are configured as outputs the logic level is driven out of the corresponding MCU pin Reset forces PTFD to all 0s but these 0s are not driven out of the corresp...

Page 166: ...that are configured as Hi Z a read returns uncertainty data Writes are latched into all bits of this register For port H pins that are configured as outputs the logic level is driven out of the corres...

Page 167: ...isabled to offer high current drive capability 1 PTE1 is enabled to offer high current drive capability 4 PTE0 PTE0 This read write bit enables the high current drive capability of PTE0 0 PTE0 is disa...

Page 168: ...7 This read write bit enables the port A pin as an output 0 Output Disabled for port A bit 7 1 Output Enabled for port A bit 7 6 PTAOE6 Output Enable for Port A Bit 6 This read write bit enables the...

Page 169: ...A bit 0 7 7 11 Port B Output Enable Register PORT_PTBOE Address 0h base 30B1h offset 30B1h Bit 7 6 5 4 3 2 1 0 Read PTBOE7 PTBOE6 PTBOE5 PTBOE4 PTBOE3 PTBOE2 PTBOE1 PTBOE0 Write Reset 0 0 0 0 0 0 0 0...

Page 170: ...r port B bit 2 1 PTBOE1 Output Enable for Port B Bit 1 This read write bit enables the port B pin as an output 0 Output Disabled for port B bit 1 1 Output Enabled for port B bit 1 0 PTBOE0 Output Enab...

Page 171: ...ut Enabled for port C bit 4 3 PTCOE3 Output Enable for Port C Bit 3 This read write bit enables the port C pin as an output 0 Output Disabled for port C bit 3 1 Output Enabled for port C bit 3 2 PTCOE...

Page 172: ...bit enables the port D pin as an output 0 Output Disabled for port D bit 5 1 Output Enabled for port D bit 5 4 PTDOE4 Output Enable for Port D Bit 4 This read write bit enables the port D pin as an ou...

Page 173: ...n as an output 0 Output Disabled for port E bit 7 1 Output Enabled for port E bit 7 6 PTEOE6 Output Enable for Port E Bit 6 This read write bit enables the port E pin as an output 0 Output Disabled fo...

Page 174: ...r port E bit 0 7 7 15 Port F Output Enable Register PORT_PTFOE Address 0h base 30B5h offset 30B5h Bit 7 6 5 4 3 2 1 0 Read PTFOE7 PTFOE6 PTFOE5 PTFOE4 PTFOE3 PTFOE2 PTFOE1 PTFOE0 Write Reset 0 0 0 0 0...

Page 175: ...bled for port F bit 2 1 PTFOE1 Output Enable for Port F Bit 1 This read write bit enables the port F pin as an output 0 Output Disabled for port F bit 1 1 Output Enabled for port F bit 1 0 PTFOE0 Outp...

Page 176: ...read write bit enables the port G pin as an output 0 Output Disabled for port G bit 0 1 Output Enabled for port G bit 0 7 7 17 Port H Output Enable Register PORT_PTHOE Address 0h base 30B7h offset 30B...

Page 177: ...tput Enabled for port H bit 0 7 7 18 Port A Input Enable Register PORT_PTAIE Address 0h base 30B8h offset 30B8h Bit 7 6 5 4 3 2 1 0 Read PTAIE7 PTAIE6 PTAIE5 0 PTAIE3 PTAIE2 PTAIE1 PTAIE0 Write Reset...

Page 178: ...rt A pin as an input 0 Input disabled for port A bit 1 1 Input enabled for port A bit 1 0 PTAIE0 Input Enable for Port A Bit 0 This read write bit enables the port A pin as an input 0 Input disabled f...

Page 179: ...B bit 3 1 Input enabled for port B bit 3 2 PTBIE2 Input Enable for Port B Bit 2 This read write bit enables the port B pin as an input 0 Input disabled for port B bit 2 1 Input enabled for port B bit...

Page 180: ...an input 0 Input disabled for port C bit 4 1 Input enabled for port C bit 4 3 PTCIE3 Input Enable for Port C Bit 3 This read write bit enables the port C pin as an input 0 Input disabled for port C b...

Page 181: ...enables the port D pin as an input 0 Input disabled for port D bit 5 1 Input enabled for port D bit 5 4 PTDIE4 Input Enable for Port D Bit 4 This read write bit enables the port D pin as an input 0 I...

Page 182: ...port E pin as an input 0 Input disabled for port E bit 7 1 Input enabled for port E bit 7 6 PTEIE6 Input Enable for Port E Bit 6 This read write bit enables the port E pin as an input 0 Input disable...

Page 183: ...bit 0 7 7 23 Port F Input Enable Register PORT_PTFIE Address 0h base 30BDh offset 30BDh Bit 7 6 5 4 3 2 1 0 Read PTFIE7 PTFIE6 PTFIE5 PTFIE4 PTFIE3 PTFIE2 PTFIE1 PTFIE0 Write Reset 0 0 0 0 0 0 0 0 PO...

Page 184: ...enabled for port F bit 2 1 PTFIE1 Input Enable for Port F Bit 1 This read write bit enables the port F pin as an input 0 Input disabled for port F bit 1 1 Input enabled for port F bit 1 0 PTFIE0 Input...

Page 185: ...rite bit enables the port G pin as an input 0 Input disabled for port G bit 0 1 Input enabled for port G bit 0 7 7 25 Port H Input Enable Register PORT_PTHIE Address 0h base 30BFh offset 30BFh Bit 7 6...

Page 186: ...for Port H Bit 0 This read write bit enables the port H pin as an input 0 Input disabled for port H bit 0 1 Input enabled for port H bit 0 7 7 26 Port Filter Register 0 PORT_IOFLT0 This register sets...

Page 187: ...30EDh offset 30EDh Bit 7 6 5 4 3 2 1 0 Read FLTH FLTG FLTF FLTE Write Reset 0 0 0 0 0 0 0 0 PORT_IOFLT1 field descriptions Field Description 7 6 FLTH Filter selection for input from PTH 00 BUSCLK 01...

Page 188: ...n for input from KBI1 00 BUSCLK 01 Select FLTDIV1 and will switch to FLTDIV3 in stop mode automatically 10 Select FLTDIV2 and will switch to FLTDIV3 in stop mode automatically 11 FLTDIV3 3 2 FLTKBI0 F...

Page 189: ...0 PORT_FCLKDIV field descriptions Field Description 7 5 FLTDIV3 Filter Division Set 3 Port Filter Division Set 3 000 LPOCLK 001 LPOCLK 2 010 LPOCLK 4 011 LPOCLK 8 100 LPOCLK 16 101 LPOCLK 32 110 LPOCL...

Page 190: ...or Hi Z these bits have no effect 0 Pullup disabled for port A bit 5 1 Pullup enabled for port A bit 5 4 Reserved This field is reserved This read only field is reserved and always has the value 0 3 P...

Page 191: ...e Reset 0 0 0 0 0 0 0 0 PORT_PTBPE field descriptions Field Description 7 PTBPE7 Pull Enable for Port B Bit 7 This control bit determines if the internal pullup device is enabled for the associated PT...

Page 192: ...0 Pullup disabled for port B bit 2 1 Pullup enabled for port B bit 2 1 PTBPE1 Pull Enable for Port B Bit 1 This control bit determines if the internal pullup device is enabled for the associated PTB p...

Page 193: ...ffect 0 Pullup disabled for port C bit 4 1 Pullup enabled for port C bit 4 3 PTCPE3 Pull Enable for Port C Bit 3 This control bit determines if the internal pullup device is enabled for the associated...

Page 194: ...o effect 0 Pullup disabled for port D bit 6 1 Pullup enabled for port D bit 6 5 PTDPE5 Pull Enable for Port D Bit 5 This control bit determines if the internal pullup device is enabled for the associa...

Page 195: ...up disabled for port D bit 0 1 Pullup enabled for port D bit 0 7 7 34 Port E Pullup Enable Register PORT_PTEPE Address 0h base 30F4h offset 30F4h Bit 7 6 5 4 3 2 1 0 Read PTEPE7 PTEPE6 PTEPE5 PTEPE4 P...

Page 196: ...it 2 This control bit determines if the internal pullup device is enabled for the associated PTE pin For port E pins that are configured as outputs or Hi Z these bits have no effect 0 Pullup disabled...

Page 197: ...for the associated PTF pin For port F pins that are configured as outputs or Hi Z these bits have no effect 0 Pullup disabled for port F bit 4 1 Pullup enabled for port F bit 4 3 PTFPE3 Pull Enable f...

Page 198: ...effect 0 Pullup disabled for port G bit 3 1 Pullup enabled for port G bit 3 2 PTGPE2 Pull Enable for Port G Bit 2 This control bit determines if the internal pullup device is enabled for the associate...

Page 199: ...ved This read only field is reserved and always has the value 0 2 PTHPE2 Pull Enable for Port H Bit 2 This control bit determines if the internal pullup device is enabled for the associated PTH pin Fo...

Page 200: ...Port data registers MC9S08PT60 Reference Manual Rev 4 08 2014 200 Freescale Semiconductor Inc...

Page 201: ...allows a lower output clock frequency to be derived The external oscillator XOSC module allows an external crystal ceramic resonator or other external clock source to produce the external reference c...

Page 202: ...TE2 MISO0 PTE3 SS0 PTE4 PTE5 PTE6 PTE7 TCLK2 PTF0 TSI12 PTF1 TSI13 PTF2 TSI14 PTF3 TSI15 PTF4 ADP12 PTF5 ADP13 PTF6 ADP14 PTF7 ADP15 PTG0 PTG1 PTG2 PTG3 PTH0 FTM2CH0 PTH1 FTM2CH1 PTH2 BUSOUT PTH6 PTH7...

Page 203: ...rol the FLL Reference divider is provided for external clock Internal reference clock has nine trim bits available Internal or external reference clocks can be selected as the clock source for the MCU...

Page 204: ...LP is provided to allow the FLL to be disabled and thus conserve power when it is not used However in some applications it may be desirable to allow the FLL to be enabled and to lock for maximum accu...

Page 205: ...by users This value is uploaded to the ICS_C3 register and ICS_C4 register during any reset initialization For finer precision trim the internal oscillator in the application and set the ICS_C4 SCFTRI...

Page 206: ...ypassed internal low power FBILP and FLL bypassed external low power FBELP modes The ICSLCLK can be selected as BDC clock 8 2 2 Modes of operation There are seven modes of operation for the ICS FEI FE...

Page 207: ...ged at anytime but the actual switch to the newly selected clock is shown by the ICS_S IREFST bit When switching between FLL engaged internal FEI and FLL engaged external FEE modes the FLL will lock a...

Page 208: ...reference clock source The FLL loop locks the frequency to the 512 times the external reference frequency as selected by the ICS_C1 RDIV bits The ICSLCLK is available for BDC communications and the e...

Page 209: ...REFS bit is written to 0 ICS_C1 RDIV bits are written to divide external reference clock to be within the range of 31 25 kHz to 39 0625 kHz BDM mode is active or ICS_C2 LP bit is written to 0 In FLL b...

Page 210: ...the MCU enters a stop state In this mode all ICS clock signals are static except in the following cases ICSIRCLK will be active in stop mode when all of the following conditions occur ICS_C1 IRCLKEN b...

Page 211: ...the FLL is not on therefore lock detect function is not applicable 8 2 3 2 External reference clock monitor In FBE FEE FEI or FBI modes if ICS_C4 CME bit is written to 1 the clock monitor is enabled I...

Page 212: ...S_C3 TRIM_VALUE_31K25HZ FLL output 16MHz TRIM_VALUE_31K25HZ is 0x90 typically 8 3 2 Initializing FBI mode The following code segment demonstrates setting ICS to FBI mode Example 8 3 2 1 FBI mode initi...

Page 213: ...ng until oscillator is ready ICS_C1 0x80 external clock reference 20MHZ to FLL output ICS_C2 0x00 BDIV 0 prescalar 1 8 3 5 External oscillator OSC The oscillator module provides the reference clock fo...

Page 214: ...k module is disabled EXTAL can be used as the input of external clock source When external clock source is not used in this mode the EXTAL can be used as GPIO or other function muxed with this pinout...

Page 215: ...refully selected to get best performance The following figure shows the typical OSC high gain mode connection MCU EXTAL XTAL RS C1 C2 X1 RF Figure 8 7 OSC high gain mode connection 8 3 5 4 Initializin...

Page 216: ...eby reducing the overall run and wait mode currents Out of reset all peripheral clocks will be enabled For lowest possible run wait currents user software should disable the clock source to any periph...

Page 217: ...0 0 0 0 0 1 0 0 ICS_C1 field descriptions Field Description 7 6 CLKS Clock Source Select Selects the clock source that controls the bus frequency The actual bus frequency depends on the value of the...

Page 218: ...f ICS is in FEI FBI or FBILP mode before entering stop 1 Reset default 8 6 2 ICS Control Register 2 ICS_C2 Address 3038h base 1h offset 3039h Bit 7 6 5 4 3 2 1 0 Read BDIV LP 0 Write Reset 0 0 1 0 0 0...

Page 219: ...reference clock frequency by controlling the internal reference clock period The bits are binary weighted In other words bit 1 adjusts twice as much as bit 0 Increasing the binary value in SCTRIM will...

Page 220: ...ny BDM mode 8 6 5 ICS Status Register ICS_S Address 3038h base 4h offset 303Ch Bit 7 6 5 4 3 2 1 0 Read LOLS LOCK 0 IREFST CLKST 0 Write Reset 0 0 0 1 0 0 0 0 ICS_S field descriptions Field Descriptio...

Page 221: ...k 1 Source of reference clock is internal clock 3 2 CLKST Clock Mode Status The CLKST bits indicate the current clock mode The CLKST bits don t update immediately after a write to the CLKS bits due to...

Page 222: ...quency range for the OSC module 0 Low frequency range of 31 25kHz 39 0625kHz 1 High frequency range of 4 20MHz 1 HGO High Gain Oscillator Select The HGO bit controls the OSC mode of operation 0 Low ga...

Page 223: ...lock gate to the FTM2 module 0 Bus clock to the FTM2 module is disabled 1 Bus clock to the FTM2 module is enabled 6 FTM1 FTM1 Clock Gate Control This bit controls the clock gate to the FTM1 module 0 B...

Page 224: ...software should disable the peripheral before disabling the clocks to the peripheral When clocks are re enabled to a peripheral the peripheral registers need to be re initialized by user software Add...

Page 225: ...ol bits to enable or disable the bus clock to the SCI SPI IIC modules Gating off the clocks to unused peripherals is used to reduce the MCU s run and wait currents NOTE User software should disable th...

Page 226: ...0 Bus clock to the SPI0 module is disabled 1 Bus clock to the SPI0 module is enabled 1 IIC IIC Clock Gate Control This bit controls the clock gate to the IIC module 0 Bus clock to the IIC module is di...

Page 227: ...This read only field is reserved and always has the value 0 3 IRQ IRQ Clock Gate Control This bit controls the clock gate to the IRQ module 0 Bus clock to the IRQ module is disabled 1 Bus clock to the...

Page 228: ...System clock gating control registers MC9S08PT60 Reference Manual Rev 4 08 2014 228 Freescale Semiconductor Inc...

Page 229: ...instructions and enhanced addressing modes were added to improve C compiler efficiency and to support a new background debug system which replaces the monitor mode of earlier M68HC08 microcontrollers...

Page 230: ...internal or external reference clock The module can select clock from the FLL or bypass the FLL as a source of the MCU system clock The selected clock source is passed through a reduced bus divider wh...

Page 231: ...PTE3 SS0 PTE4 PTE5 PTE6 PTE7 TCLK2 PTF0 TSI12 PTF1 TSI13 PTF2 TSI14 PTF3 TSI15 PTF4 ADP12 PTF5 ADP13 PTF6 ADP14 PTF7 ADP15 PTG0 PTG1 PTG2 PTG3 PTH0 FTM2CH0 PTH1 FTM2CH1 PTH2 BUSOUT PTH6 PTH7 PTE0 SPS...

Page 232: ...non volatile data Non volatile memory NVM includes Flash memory MC9S08PT60 60 864 bytes 119 sectors of 512 bytes1 MC9S08PT32 32 768 bytes 64 sectors of 512 bytes EEPROM memory MC9S08PT60 256 bytes 12...

Page 233: ...ection The 16 bit code is calculated for 8 bit of data at a time and provides a simple check for all accessible memory locations in flash and RAM The following figure shows the device block diagram hi...

Page 234: ...MOSI0 PTE2 MISO0 PTE3 SS0 PTE4 PTE5 PTE6 PTE7 TCLK2 PTF0 TSI12 PTF1 TSI13 PTF2 TSI14 PTF3 TSI15 PTF4 ADP12 PTF5 ADP13 PTF6 ADP14 PTF7 ADP15 PTG0 PTG1 PTG2 PTG3 PTH0 FTM2CH0 PTH1 FTM2CH1 PTH2 BUSOUT P...

Page 235: ...utputs generation of triggers and fault inputs Each FTM module has independent external clock input The following table summarizes the external signals of FTM modules Table 9 1 FTM module external sig...

Page 236: ...I0 PTE2 MISO0 PTE3 SS0 PTE4 PTE5 PTE6 PTE7 TCLK2 PTF0 TSI12 PTF1 TSI13 PTF2 TSI14 PTF3 TSI15 PTF4 ADP12 PTF5 ADP13 PTF6 ADP14 PTF7 ADP15 PTG0 PTG1 PTG2 PTG3 PTH0 FTM2CH0 PTH1 FTM2CH1 PTH2 BUSOUT PTH6...

Page 237: ...o PTA6 Fault 2 is connected to PTA7 Fault 3 is not used Please refer to System interconnection FTM2 supports seven FTM triggers including an initialization trigger and six channel triggers to other mo...

Page 238: ...1P5 PTD6 KBI1P6 RxD2 PTD7 KBI1P7 TxD2 PTE1 MOSI0 PTE2 MISO0 PTE3 SS0 PTE4 PTE5 PTE6 PTE7 TCLK2 PTF0 TSI12 PTF1 TSI13 PTF2 TSI14 PTF3 TSI15 PTF4 ADP12 PTF5 ADP13 PTF6 ADP14 PTF7 ADP15 PTG0 PTG1 PTG2 PT...

Page 239: ...terrupt This module can be used for time of day calendar or any task scheduling functions It can also serve as a cyclic wakeup from low power modes without external components RTC overflow trigger can...

Page 240: ...SI0 PTE2 MISO0 PTE3 SS0 PTE4 PTE5 PTE6 PTE7 TCLK2 PTF0 TSI12 PTF1 TSI13 PTF2 TSI14 PTF3 TSI15 PTF4 ADP12 PTF5 ADP13 PTF6 ADP14 PTF7 ADP15 PTG0 PTG1 PTG2 PTG3 PTH0 FTM2CH0 PTH1 FTM2CH1 PTH2 BUSOUT PTH6...

Page 241: ...nsmit and receive within the same SCI use a common baud rate and each SCI module has a separate baud rate generator This SCI system offers many advanced features not commonly found on other asynchrono...

Page 242: ...ISO0 PTE3 SS0 PTE4 PTE5 PTE6 PTE7 TCLK2 PTF0 TSI12 PTF1 TSI13 PTF2 TSI14 PTF3 TSI15 PTF4 ADP12 PTF5 ADP13 PTF6 ADP14 PTF7 ADP15 PTG0 PTG1 PTG2 PTG3 PTH0 FTM2CH0 PTH1 FTM2CH1 PTH2 BUSOUT PTH6 PTH7 PTE0...

Page 243: ...llowing table lists all the FTM registers this device has Table 9 2 FTM registers Registers x 0 1 2 FTM0 FTM1 FTM2 FTMx_SC Y Y Y FTM2_CNTH Y Y Y FTMx_CNTL Y Y Y FTMx_MODH Y Y Y FTMx_MODL Y Y Y FTMx_C0...

Page 244: ...FTMx_FLTFILTER N N Y FTMx_FLTCTRL N N Y 9 9 2 8 Bit Serial Peripheral Interface 8 bit SPI This MCU contains an 8 bit serial peripheral interface SPI0 module which provides for full duplex synchronous...

Page 245: ...PTE3 SS0 PTE4 PTE5 PTE6 PTE7 TCLK2 PTF0 TSI12 PTF1 TSI13 PTF2 TSI14 PTF3 TSI15 PTF4 ADP12 PTF5 ADP13 PTF6 ADP14 PTF7 ADP15 PTG0 PTG1 PTG2 PTG3 PTH0 FTM2CH0 PTH1 FTM2CH1 PTH2 BUSOUT PTH6 PTH7 PTE0 SPSC...

Page 246: ...ial communication between the MCU and peripheral devices These peripheral devices can include other microcontrollers analog to digital converters shift registers sensors memories etc The following fig...

Page 247: ...TE3 SS0 PTE4 PTE5 PTE6 PTE7 TCLK2 PTF0 TSI12 PTF1 TSI13 PTF2 TSI14 PTF3 TSI15 PTF4 ADP12 PTF5 ADP13 PTF6 ADP14 PTF7 ADP15 PTG0 PTG1 PTG2 PTG3 PTH0 FTM2CH0 PTH1 FTM2CH1 PTH2 BUSOUT PTH6 PTH7 PTE0 SPSCK...

Page 248: ...r integrated circuit I2C module for communication with other integrated circuits The following figure shows the device block diagram highlighting I2C module and pins SCI0 infrared functions MC9S08PT60...

Page 249: ...SO0 PTE3 SS0 PTE4 PTE5 PTE6 PTE7 TCLK2 PTF0 TSI12 PTF1 TSI13 PTF2 TSI14 PTF3 TSI15 PTF4 ADP12 PTF5 ADP13 PTF6 ADP14 PTF7 ADP15 PTG0 PTG1 PTG2 PTG3 PTH0 FTM2CH0 PTH1 FTM2CH1 PTH2 BUSOUT PTH6 PTH7 PTE0...

Page 250: ...ion within an integrated microcontroller system on chip The ADC channel assignments alternate clock function and hardware trigger function are configured as described following sections The following...

Page 251: ...0 PTE3 SS0 PTE4 PTE5 PTE6 PTE7 TCLK2 PTF0 TSI12 PTF1 TSI13 PTF2 TSI14 PTF3 TSI15 PTF4 ADP12 PTF5 ADP13 PTF6 ADP14 PTF7 ADP15 PTG0 PTG1 PTG2 PTG3 PTH0 FTM2CH0 PTH1 FTM2CH1 PTH2 BUSOUT PTH6 PTH7 PTE0 SP...

Page 252: ...01000 AD8 PTC0 ADP8 01001 AD9 PTC1 ADP9 01010 AD10 PTC2 ADP10 01011 AD11 PTC3 ADP11 01100 AD12 PTF4 ADP12 01101 AD13 PTF5 ADP13 01110 AD14 PTF6 ADP14 01111 AD15 PTF7 ADP15 10000 AD16 VSS 10001 AD17 VS...

Page 253: ...are trigger The ADC hardware trigger is selectable from MTIM0 overflow RTC overflow FTM2 match trigger with 8 bit programmable delay or FTM2 init trigger with 8 bit programmable delay The MCU can be c...

Page 254: ...ope for both hot and cold In application code you can calculate the temperature as detailed above and determine if it is above or below 25 C After you have determined whether the temperature is above...

Page 255: ...RxD2 PTD7 KBI1P7 TxD2 PTE1 MOSI0 PTE2 MISO0 PTE3 SS0 PTE4 PTE5 PTE6 PTE7 TCLK2 PTF0 TSI12 PTF1 TSI13 PTF2 TSI14 PTF3 TSI15 PTF4 ADP12 PTF5 ADP13 PTF6 ADP14 PTF7 ADP15 PTG0 PTG1 PTG2 PTG3 PTH0 FTM2CH0...

Page 256: ...ACMP continues to operate in stop3 mode if enabled If ACMP_SC ACOPE is enabled comparator output will operate as in the normal operating mode and will control ACMPO pin The MCU is brought out of stop...

Page 257: ...up to 16 keyboard interrupt inputs grouped in two KBI modules available depending on packages The following figure shows the device block diagram with the KBI modules and pins highlighted 9 11 Chapter...

Page 258: ...MISO0 PTE3 SS0 PTE4 PTE5 PTE6 PTE7 TCLK2 PTF0 TSI12 PTF1 TSI13 PTF2 TSI14 PTF3 TSI15 PTF4 ADP12 PTF5 ADP13 PTF6 ADP14 PTF7 ADP15 PTG0 PTG1 PTG2 PTG3 PTH2 BUSOUT PTH6 PTH7 PTE0 SPSCK0 TCLK1 PTA2 KBI0P2...

Page 259: ...ounter this module allows users to detect 0 01 pF change on a 100 pF electrode Also the TSI module provides special functions of current source swap pseudo noise generation and separate charge dischar...

Page 260: ...O0 PTE3 SS0 PTE4 PTE5 PTE6 PTE7 TCLK2 PTF0 TSI12 PTF1 TSI13 PTF2 TSI14 PTF3 TSI15 PTF4 ADP12 PTF5 ADP13 PTF6 ADP14 PTF7 ADP15 PTG0 PTG1 PTG2 PTG3 PTH0 FTM2CH0 PTH1 FTM2CH1 PTH2 BUSOUT PTH6 PTH7 PTE0 S...

Page 261: ...TC6 TSI8 1001 TSI9 PTC7 TSI9 0010 TSI10 PTD2 TSI10 1011 TSI11 PTD3 TSI11 1100 TSI12 PTF0 TSI12 1101 TSI13 PTF1 TSI13 1110 TSI14 PTF2 TSI14 1111 TSI15 PTF3 TSI15 9 11 2 2 Hardware trigger The TSI modul...

Page 262: ...Human machine interfaces HMI MC9S08PT60 Reference Manual Rev 4 08 2014 262 Freescale Semiconductor Inc...

Page 263: ...M68HC05 and M68HC08 families 16 bit stack pointer any size stack anywhere in 64 KB CPU address space 16 bit index register H X with powerful indexed addressing modes 8 bit accumulator A Many instructi...

Page 264: ...five CPU registers CPU registers are not part of the memory map SP PC CARRY ZERO NEGATIVE INTERRUPT MASK HALF CARRY FROM BIT 3 ACCUMULATOR A INDEX REGISTER X INDEX REGISTER H STACK POINTER PROGRAM COU...

Page 265: ...the earlier M68HC05 family H is forced to 0x00 during reset Reset has no effect on the contents of X 10 2 3 Stack Pointer SP This 16 bit address pointer register points at the next available location...

Page 266: ...instructions BGT BGE BLE and BLT use the overflow flag 0 No overflow 1 Overflow 4 H Half Carry Flag The CPU sets the half carry flag when a carry occurs between accumulator bits 3 and 4 during an add...

Page 267: ...HCS08 V6 memory status and control registers and input output I O ports share a single 64 KB CPU address space This arrangement means that the same instructions that access variables in RAM can also...

Page 268: ...added to the current contents of the program counter which causes program execution to continue at the branch destination address If a branch condition is false the CPU executes the next instruction 1...

Page 269: ...s is assumed to be zero During execution the CPU combines the value 55 from the instruction with the assumed value of 00 to form the address 0055 which is then used to access the data to be loaded int...

Page 270: ...dexed No Offset with Post Increment IX Instructions using the indexed no offset with post increment addressing mode are two byte instructions that address the operands and then increment the Index reg...

Page 271: ...st significant byte of the 16 bit offset the second byte is the least significant byte of the 16 bit offset As with direct and extended addressing most assemblers determine the shortest form of indexe...

Page 272: ...k th element a an n element table The table can begin anywhere and can extend anywhere in memory The k value would typically be in the stack pointer register and the address of the beginning of the ta...

Page 273: ...the time spent in stop mode and to issue a signal to wake up the target MCU when it is time to resume processing Unlike the earlier M68HC05 and M68HC08 MCUs the HCS08 V6 can be configured to keep a mi...

Page 274: ...in either stop or wait mode The BACKGROUND command can be used to wake the CPU from wait mode and enter active background mode 10 4 3 Background mode Background instruction BGND is not used in normal...

Page 275: ...ode to return to the user s application program GO The active background mode is used to program a bootloader or user application program into the flash program memory before the MCU is operated in ru...

Page 276: ...ed during the stacking cycles of interrupt service routines 6 Data accesses to either secure or non secure memory are allowed when the current instruction is tagged as secure 7 BDC accesses to non sec...

Page 277: ...hen the sequence to determine whether the reset came from an internal source is done and when the reset pin is no longer asserted At the conclusion of a reset event the CPU performs a 6 cycle sequence...

Page 278: ...as part of the interrupt sequence The user must use a PSHH instruction at the beginning of the service routine to save H and then use a PULH instruction just before the RTI that ends the interrupt se...

Page 279: ...bit value IMM AF ii 2 AND opr8i 0 IMM A4 ii 2 AND opr8a 0 DIR B4 dd 3 AND opr16a 0 EXT C4 hh ll 4 AND oprx16 X 0 IX2 D4 ee ff 4 AND oprx8 X Logical AND A A M 0 IX1 E4 ff 3 AND X 0 IX F4 3 AND oprx16...

Page 280: ...ater Than Signed Operands Branch if Z N V 0 REL 92 rr 3 BHCC rel Branch if Half Carry Bit Clear Branch if H 0 REL 28 rr 3 BHCS rel Branch if Half Carry Bit Set Branch if H 1 REL 29 rr 3 BHI rel Branch...

Page 281: ...3 BNE rel Branch if Not Equal Branch if Z 0 REL 26 rr 3 BPL rel Branch if Plus Branch if N 0 REL 2A rr 3 BRA rel Branch Always No Test REL 20 rr 3 DIR b0 01 dd rr 5 DIR b1 03 dd rr 5 DIR b2 05 dd rr 5...

Page 282: ...pr8a rel Branch if A M DIR 31 dd rr 5 CBEQA opr8i rel Branch if A M IMM 41 ii rr 4 CBEQX opr8i rel Compare and Branch if Equal Branch if X M IMM 51 ii rr 4 CBEQ oprx8 X rel Branch if A M IX1 61 ff rr...

Page 283: ...8 SP M M 0xFF M 0 1 SP1 9E63 ff 6 CPHX opr16a EXT 3E hh ll 6 CPHX opr16i IMM 65 jj kk 3 CPHX opr8a Compare Index Register H X with Memory H X M M 0x0001 CCR Updated But Operands Not Changed DIR 75 dd...

Page 284: ...opr16a 0 EXT C8 hh ll 4 EOR oprx16 X 0 IX2 D8 ee ff 4 EOR oprx8 X Exclusive OR Memory with Accumulator A A M 0 IX1 E8 ff 3 EOR X 0 IX F8 3 EOR oprx16 SP 0 SP2 9ED8 ee ff 5 EOR oprx8 SP 0 SP1 9EE8 ff 4...

Page 285: ...d Index Register H X from Memory H X M M 0x0001 0 IX 9EAE 5 LDHX oprx16 X 0 IX2 9EBE ee ff 6 LDHX oprx8 X 0 IX1 9ECE ff 5 LDHX oprx8 SP 0 SP1 9EFE ff 5 LDX opr8i 0 IMM AE ii 2 LDX opr8a 0 DIR BE dd 3...

Page 286: ...x00 X INH 50 1 NEG oprx8 X M M 0x00 M IX1 60 ff 5 NEG X M M 0x00 M IX 70 4 NEG oprx8 SP M M 0x00 M SP1 9E60 ff 6 NOP No Operation Uses 1 Bus Cycle INH 9D 1 NSA Nibble Swap Accumulator A A 3 0 A 7 4 IN...

Page 287: ...oprx8 SP SP1 9E69 ff 6 ROR opr8a DIR 36 dd 5 RORA INH 46 1 RORX INH 56 1 ROR oprx8 X Rotate Right through Carry LSB C C MSB IX1 66 ff 5 ROR X IX 76 4 ROR oprx8 SP SP1 9E66 ff 6 RSP Reset Stack Pointer...

Page 288: ...3 STA X Store Accumulator in Memory M A 0 IX F7 2 STA oprx16 SP 0 SP2 9ED7 ee ff 5 STA oprx8 SP 0 SP1 9EE7 ff 4 STHX opr8a 0 DIR 35 dd 4 STHX opr16a Store H X Index Reg M M 0x0001 H X 0 EXT 96 hh ll 5...

Page 289: ...upt Vector Low Byte TAP Transfer Accumulator to CCR CCR A INH 84 1 TAX Transfer Accumulator to X Index Register Low X A INH 97 1 TPA Transfer CCR to Accumulator A CCR INH 85 1 TST opr8a M 0x00 0 DIR 3...

Page 290: ...Operation Description Effect on CCR Address Mode Opcode Operand Bus Cycles V H I N Z C WAIT Enable Interrupts Wait for Interrupt I bit 0 Halt CPU 0 INH 8F 3 Instruction Set Summary MC9S08PT60 Referen...

Page 291: ...le as falling edge sensitivity only rising edge sensitivity only both falling edge and low level sensitivity both rising edge and high level sensitivity One software enabled keyboard interrupt Exit fr...

Page 292: ...errupt must be enabled KBI_SC KBIE 1 before executing the Stop instruction allowing the KBI to continue to operate while the MCU is in Stop3 mode An enabled KBI pin KBI_PE KBIPEn 1 can be used to brin...

Page 293: ...the absolute address assignments for all KBI registers This section refers to registers and control bits only by their names Some MCUs may have more than one KBI so register names include placeholder...

Page 294: ...cted 1 KBI interrupt request detected 2 KBACK KBI Acknowledge Writing a 1 to KBACK is part of the flag clearing mechanism 1 KBIE KBI Interrupt Enable KBIE determines whether a KBI interrupt is enabled...

Page 295: ...s called a keyboard interrupt module because originally it was designed to simplify the connection and use of row column matrices of keyboard switches However these inputs are also useful as extra ext...

Page 296: ...resented to the MPU Clearing of KBIx_SC KBF is accomplished by writing a 1 to KBIx_SC KBACK 11 5 2 Edge and level sensitivity A valid edge or level on an enabled KBI pin will set KBIx_SC KBF If KBIx_S...

Page 297: ...by clearing KBIx_SC KBIE 2 Enable the KBI polarity by setting the appropriate KBIx_ES KBEDGn bits 3 Before using internal pullup resistors configure the associated bits in PORT_PTxPE 4 Enable the KBI...

Page 298: ...Functional Description MC9S08PT60 Reference Manual Rev 4 08 2014 298 Freescale Semiconductor Inc...

Page 299: ...e TPM The FlexTimer extends the functionality to meet the demands of motor control digital lighting solutions and power conversion while providing low cost and backwards compatibility with the TPM mod...

Page 300: ...o determine which registers are updated with this user defined data 12 1 2 Features The FTM features include Selectable FTM source clock Source clock can be the system clock the fixed frequency clock...

Page 301: ...rrupt when the fault condition is detected Synchronized loading of write buffered FTM registers Write protection for critical registers Backwards compatible with TPM Testing of input captures for a st...

Page 302: ...n is the channel number 0 7 The following figure shows the FTM structure The central component of the FTM is the 16 bit counter with programmable initial and final values and its counting can be up or...

Page 303: ...Deadtime insertion Fault control Polarity control Output mask COMP MS1B MS1A ELS1B ELS1A Input capture mode logic DECAPEN COMBINE CPWMS CH1F CH1IE channel 1 interrupt channel 6 interrupt DTEN DTPS 1...

Page 304: ...12 2 2 CHn FTM channel n I O pin Each FTM channel can be configured to operate either as input or output The direction associated with each channel input or output is selected according to the mode as...

Page 305: ...ion Note Do not write to the FTM specific registers second set registers when FTMEN 0 12 3 2 Register descriptions This section consists of register descriptions in address order NOTE Not all the regi...

Page 306: ...Initial Value Low FTM0_CNTINL 8 R W 00h 12 3 12 317 39 Capture and Compare Status FTM0_STATUS 8 R W 00h 12 3 13 317 3A Features Mode Selection FTM0_MODE 8 R W 04h 12 3 14 319 3B Synchronization FTM0_...

Page 307: ...ue High FTM1_C5VH 8 R W 00h 12 3 9 315 46 Channel Value Low FTM1_C5VL 8 R W 00h 12 3 10 316 47 Counter Initial Value High FTM1_CNTINH 8 R W 00h 12 3 11 316 48 Counter Initial Value Low FTM1_CNTINL 8 R...

Page 308: ...8 R W 00h 12 3 9 315 30D3 Channel Value Low FTM2_C4VL 8 R W 00h 12 3 10 316 30D4 Channel Status and Control FTM2_C5SC 8 R W 00h 12 3 8 312 30D5 Channel Value High FTM2_C5VH 8 R W 00h 12 3 9 315 30D6...

Page 309: ...reading the SC register while TOF is set and then writing a 0 to TOF bit Writing a 1 to TOF has no effect If another FTM overflow occurs between the read and write operations the write operation has...

Page 310: ...ches the contents of both bytes into a buffer where they remain latched until the other half is read This allows coherent 16 bit reads in either big endian or little endian order which makes this more...

Page 311: ...nd the next value of FTM counter depends on the selected counting method Counter Writing to either byte latches the value into a buffer The register is updated with the value of their write buffer acc...

Page 312: ...Bit 7 6 5 4 3 2 1 0 Read MOD_L Write Reset 0 0 0 0 0 0 0 0 FTMx_MODL field descriptions Field Description MOD_L Low byte of the modulo value 12 3 8 Channel Status and Control FTMx_CnSC CnSC contains t...

Page 313: ...tch up X1 Low true pulses set Output on match up 1 0 XX 10 Combine PWM High true pulses set on channel n match and clear on channel n 1 match X1 Low true pulses clear on channel n match and set on cha...

Page 314: ...he channel logic Its functionality is dependent on the channel mode See the table in the register description MSB is write protected It can be written only when MODE WPDIS 1 4 MSA Channel Mode Select...

Page 315: ...registers are updated with the value of their write buffer according to Update of the registers with write buffers If MODE FTMEN 0 this write coherency mechanism may be manually reset by writing to th...

Page 316: ...es the value into a buffer The registers are updated with the value of their write buffer When BDM is active the write coherency mechanism is frozen such that the buffer latches remain in the state th...

Page 317: ...channel for software convenience Each CHnF bit in STATUS is a mirror of CHnF bit in CnSC All CHnF bits can be checked using only one read of STATUS All CHnF bits can be cleared by reading STATUS foll...

Page 318: ...6 CH6F Channel 6 Flag See the register description 0 No channel event has occurred 1 A channel event has occurred 5 CH5F Channel 5 Flag See the register description 0 No channel event has occurred 1 A...

Page 319: ...set 0 0 0 0 0 1 0 0 FTMx_MODE field descriptions Field Description 7 FAULTIE Fault Interrupt Enable Enables the generation of an interrupt when a fault is detected by FTM and the FTM fault control is...

Page 320: ...written to WPEN WPDIS is set when WPEN bit is read as a 1 and then 1 is written to WPDIS Writing 0 to WPDIS has no effect 0 Write protection is enabled 1 Write protection is disabled 1 INIT Initialize...

Page 321: ...er Selects the software trigger as the PWM synchronization trigger The software trigger occurs when a 1 is written to SWSYNC bit 0 Software trigger is not selected 1 Software trigger is selected 6 TRI...

Page 322: ...their write buffer contents following a PWM synchronization event If CNTMAX is enabled the registers are updated when the FTM counter reaches its maximum value MOD 0 The maximum boundary cycle is dis...

Page 323: ...alue is 1 3 CH3OI Channel 3 Output Initialization Value Selects the value that is forced into the channel output when the initialization occurs 0 The initialization value is 0 1 The initialization val...

Page 324: ...is forced to its inactive state 6 CH6OM Channel 6 Output Mask Defines if the channel output is masked forced to its inactive state or unmasked it continues to operate normally 0 Channel output is not...

Page 325: ...put Mask Defines if the channel output is masked forced to its inactive state or unmasked it continues to operate normally 0 Channel output is not masked It continues to operate normally 1 Channel out...

Page 326: ...MODE FTMEN 1 and DECAPEN 1 DECAP bit is cleared automatically by hardware if dual edge capture one shot mode is selected and when the capture of channel n 1 event is made 0 The dual edge captures are...

Page 327: ...elects the division factor of the system clock This prescaled clock is used by the deadtime counter DTPS is write protected It can be written only when MODE WPDIS 1 0x Divide the system clock by 1 10...

Page 328: ...the earlier TRIGF 0 No channel trigger was generated 1 A channel trigger was generated 6 INITTRIGEN Initialization Trigger Enable Enables the generation of the trigger when the FTM counter is equal t...

Page 329: ...eneration of the channel trigger is enabled 12 3 21 Channels Polarity FTMx_POL This register defines the output polarity of the FTM channels NOTE The safe value that is driven in a channel output when...

Page 330: ...of the channel output This field is write protected It can be written only when MODE WPDIS 1 0 The channel polarity is active high 1 The channel polarity is active low 2 POL2 Channel 2 Polarity Define...

Page 331: ...Enable The WPEN bit is the negation of the WPDIS bit WPEN is set when 1 is written to it WPEN is cleared when WPEN bit is read as a 1 and then 1 is written to WPDIS Writing 0 to WPEN has no effect 0...

Page 332: ...e FMS register while FAULTFn is set and then writing a 0 to FAULTFn FAULTF while there is no existing fault condition at the fault input n Writing a 1 to FAULTFn has no effect FAULTFn bit is also clea...

Page 333: ...annel input The filter is disabled when the value is zero CHevenFVAL Input Filter for Even Channel Selects the filter value for the even numbered channel input The filter is disabled when the value is...

Page 334: ...is write protected It can be written only when MODE WPDIS 1 0 Fault input filter is disabled 1 Fault input filter is enabled 6 FFLTR2EN Fault Input 2 Filter Enable Enables the filter for the fault inp...

Page 335: ...Enable Enables the fault input This field is write protected It can be written only when MODE WPDIS 1 0 Fault input is disabled 1 Fault input is enabled 0 FAULT0EN Fault Input 0 Enable Enables the fau...

Page 336: ...isable the FTM counter After any MCU reset CLKS 1 0 0 0 so no clock source is selected The CLKS 1 0 bits may be read or written at any time Disabling the FTM counter by writing 0 0 to the CLKS 1 0 bit...

Page 337: ...ler counter PS 2 0 001 CNTINH L 0x0000 MODH L 0x0003 Figure 12 187 Example of the prescaler counter 12 4 3 Counter The FTM has a 16 bit counter that is used by the channels either for input or output...

Page 338: ...L CNTINH L 0x0001 x period of FTM counter clock Figure 12 188 Example of FTM up and signed counting If CNTINH L 0x0000 the FTM counting is equivalent to TPM up counting that is up and unsigned countin...

Page 339: ...values of CNTINH L and MODH L that do not satisfy this criteria can result in unpredictable behavior MODH L CNTINH L is a redundant condition In this case the FTM counter is always equal to MODH L an...

Page 340: ...the final value of the count The value of CNTINH L is loaded into the FTM counter and the counter increments until the value of MODH L is reached at which point the counter is decremented until it re...

Page 341: ...s are not guaranteed 12 4 3 3 Free running counter If FTMEN 0 and MODH L 0x0000 or MODH L 0xFFFF the FTM counter is a free running counter In this case the FTM counter runs free from 0x0000 through 0x...

Page 342: ...annel interrupt is generated if enabled by CHnIE 1 See the following figure When a channel is configured for input capture the CHn pin is an edge sensitive input ELSnB ELSnA control bits determine whi...

Page 343: ...input Note Input capture mode is available only with CNTINH L 0x0000 Input capture mode with CNTINH L 0x0000 is not recommended and its results are not guaranteed 12 4 4 1 Filter for input capture mod...

Page 344: ...three rising edges of the system clock If CHnFVAL 3 0 0000 then the input signal is delayed by the minimum pulse width CHnFVAL 3 0 4 system clocks plus a further four rising edges of the system clock...

Page 345: ...n match channel n match CNTH L MODH L 0x0005 CnVH L 0x0003 CHnF bit Figure 12 196 Example of the output compare mode when the match toggles the channel output TOF bit 0 1 1 1 2 2 3 3 4 4 5 5 0 0 prev...

Page 346: ...is determined by CnVH L CNTINH L The CHnF bit is set and the channel n interrupt is generated if CHnIE 1 at the channel n match FTM counter CnVH L that is at the end of the pulse width This type of P...

Page 347: ...FTM counter CnVH L See the following figure TOF bit CHnF bit CNTH L channel n output MODH L 0x0008 CnVH L 0x0005 counter overflow channel n match counter overflow 0 1 2 3 4 5 6 7 8 0 1 2 previous valu...

Page 348: ...h centers for all channels are aligned with the value of CNTINH L The other channel modes are not compatible with the up down counter CPWMS 1 Therefore all FTM channels must be used in CPWM mode when...

Page 349: ...h ELSnB ELSnA X 1 If CnVH L 0x0000 or CnVH L is a negative value that is CnVH 7 1 then the channel n output is a 0 duty cycle CPWM signal and CHnF bit is not set even when there is the channel n match...

Page 350: ...orced low at the beginning of the period FTM counter CNTINH L and at the channel n 1 match FTM counter C n 1 VH L It is forced high at the channel n match FTM counter C n VH L See the following figure...

Page 351: ...el n output with ELSnB ELSnA 1 0 channel n output with ELSnB ELSnA X 1 MODH L C n VH L Figure 12 207 Channel n output if CNTIN C n V MOD and C n 1 V MOD FTM counter CNTINH L C n 1 VH L channel n outpu...

Page 352: ...and C n V is almost equal to CNTIN and C n 1 V MOD FTM counter CNTINH L C n 1 VH L not fully 100 duty cycle channel n output with ELSnB ELSnA 1 0 channel n output with ELSnB ELSnA X 1 not fully 0 duty...

Page 353: ...V and C n 1 V are not between CNTIN and MOD FTM counter CNTINH L C n 1 VH L C n VH L 0 duty cycle channel n output with ELSnB ELSnA 1 0 channel n output with ELSnB ELSnA X 1 100 duty cycle MODH L Figu...

Page 354: ...LSnB ELSnA X 1 100 duty cycle 0 duty cycle MODH L C n 1 VH L C n VH L Figure 12 214 Channel n output if C n V C n 1 V MOD channel n match is ignored FTM counter CNTINH L C n 1 VH L channel n output wi...

Page 355: ...12 216 Channel n output if C n V CNTIN and CNTIN C n 1 V MOD C n 1 VH L channel n output with ELSnB ELSnA X 1 FTM counter channel n output with ELSnB ELSnA 1 0 C n VH L MODH L CNTINH L Figure 12 217 C...

Page 356: ...Figure 12 218 Channel n output if C n V MOD and CNTIN C n 1 V MOD C n VH L CNTINH L channel n output with ELSnB ELSnA X 1 channel n output with ELSnB ELSnA 1 0 FTM counter C n 1 VH L MODH L Figure 12...

Page 357: ...of the PWM signal second edge when the channel n 1 match occurs that is FTM counter C n 1 VH L So the combine mode allows to generate asymmetrical PWM signals 12 4 9 Complementary mode The complementa...

Page 358: ...lementary mode with ELSnB ELSnA X 1 12 4 10 Update of the registers with write buffers This section describes the updating of registers that have write buffers 12 4 10 1 CNTINH L registers CNTINH L re...

Page 359: ...TMEN bit If CLKS 1 0 0 0 and FTMEN 0 then CnVH L registers are updated according to the selected mode If the selected mode is output compare mode then CnVH L registers are updated after their second b...

Page 360: ...ite buffers It is also possible to force the FTM counter to its initial value and update the CHnOM bits in OUTMASK using PWM synchronization Note PWM synchronization is available only in combine mode...

Page 361: ...hat clears the SWSYNC bit then the synchronization is made using this trigger event and the SWSYNC bit remains set because of the last write For example if PWMSYNC 0 and REINIT 0 and there is a softwa...

Page 362: ...s from CNTINH L 0x0001 to CNTINH L If CNTMAX 1 then the boundary cycle is the MODH L value MODH L and CnVH L registers are updated when the FTM counter reaches the MODH L value MODH L is reached when...

Page 363: ...ted boundary cycle after an enabled trigger event takes place If the trigger event was a software trigger then the SWSYNC bit is cleared on the next selected boundary cycle See the following figure SW...

Page 364: ...event If the trigger event was a software trigger then the SWSYNC bit is cleared See the following figure SWSYNC bit system clock MODH L registers are updated if both bytes were written software trig...

Page 365: ...e SWSYNC bit system clock selected boundary cycle MODH L registers are updated if both bytes were written software trigger event write 1 to SWSYNC bit Figure 12 229 MODH L synchronization when PWMSYNC...

Page 366: ...SYNCHOM 1 and PWMSYNC 0 then this synchronization is made on the next enabled trigger event If the trigger event was a software trigger then the SWSYNC bit is cleared on the next selected boundary cy...

Page 367: ...12 233 CHnOM Synchronization when SYNCHOM 1 PWMSYNC 1 and a hardware trigger was used 12 4 11 7 FTM counter synchronization The FTM counter synchronization occurs when the FTM counter is updated with...

Page 368: ...o TRIG0 bit Figure 12 235 FTM counter synchronization when REINIT 1 PWMSYNC 0 and a hardware trigger was used If REINIT 1 and PWMSYNC 1 then this synchronization is made on the next enabled hardware t...

Page 369: ...when the enabled hardware or software trigger occurs 1 X X 1 0 X MODH L are updated with their write buffer contents when the counter reaches its maximum value after the enabled software trigger has o...

Page 370: ...TMASK is updated with its write buffer contents when the enabled hardware or software trigger occurs 1 X 1 X X X OUTMASK is updated with its write buffer contents when the enabled hardware trigger occ...

Page 371: ...he channel n 1 output remains low for the duration of the deadtime delay after which the channel n 1 output will have a rising edge For POL n 1 POL n 1 1 and deadtime enabled a falling edge on the out...

Page 372: ...and the deadtime delay is greater than or equal to the channel n duty cycle C n 1 VH L C n VH L system clock then the channel n output is always the inactive value POL n bit value and the deadtime de...

Page 373: ...n 1 output before deadtime insertion channel n 1 output after deadtime insertion Figure 12 240 Example of the deadtime insertion ELSnB ELSnA 1 0 POL n 0 and POL n 1 0 when the deadtime delay Is compa...

Page 374: ...ts to be available in the channel n output channel n output is disabled Figure 12 241 Output mask The following table shows the output mask result before the polarity control Table 12 247 Output mask...

Page 375: ...y FFVAL 3 0 bits system clock is regarded as a glitch and is not passed on to the edge detector The fault input n filter is disabled when the FFVAL 3 0 bits are zero or when FAULTnEN 0 In this case th...

Page 376: ...n and the channel n 1 is forced to the value of POL n 1 The fault interrupt is generated when FAULTF 1 and FAULTIE 1 This interrupt request remains set until Software clears the FAULTF bit by reading...

Page 377: ...nabled when the FAULTF bit is cleared and a new PWM cycle begins See the following figure It is possible to manually clear a fault by clearing the FAULTF bit and enable disabled channels regardless of...

Page 378: ...n output polarity If POLn 0 the channel n output polarity is active high one is the active state zero is the inactive state If POLn 1 the channel n output polarity is active low zero is the active st...

Page 379: ...Figure 12 246 FTM features priority 12 4 18 Channel trigger output The channel trigger output is generated if FTMEN 1 and one or more channels were selected by the CHjTRIG bit where j 0 1 2 3 4 or 5...

Page 380: ...gure 12 247 Match triggers Note Match trigger is available only in combine mode 12 4 19 Initialization trigger If INITTRIGEN 1 the FTM generates a trigger when the FTM counter is updated with the CNTI...

Page 381: ...000 MODH L 0x000F Figure 12 250 Initialization trigger is generated when there is the FTM counter synchronization If CNTH L CNTINH L CLKS 1 0 0 0 and a value different from zero is written to CLKS 1 0...

Page 382: ...rectly the FTM counter see the following figure After both bytes were written independent of the order all CnVH L registers are updated with the value that was written to CNTH L registers and CHnF bit...

Page 383: ...1054 0x1055 0x1056 0x7856 0x78AC 0x78AE 0x78AF 0x78B0 write 0x78 write 0xAC 0x78AC 0x0300 Figure 12 252 Capture test mode 12 4 21 Dual edge capture mode The dual edge capture mode is selected if FTMEN...

Page 384: ...e width measurement In the dual edge capture mode only channel n input is used and channel n 1 input is ignored If the selected edge by channel n bits is detected at channel n input then CH n F bit is...

Page 385: ...s When this bit is cleared both edges were captured and the captured values are ready for reading in the C n VH L and C n 1 VH L registers Similarly when the CH n 1 F bit is set both edges were captur...

Page 386: ...ity pulse width is measured The pulse width measurement can be made in one shot capture mode One shot capture mode or continuous capture mode Continuous capture mode The following figure shows an exam...

Page 387: ...polarity pulse width measurement The following figure shows an example of the dual edge capture continuous mode used to measure the positive polarity pulse width The DECAPEN bit selects the dual edge...

Page 388: ...is measured If both channels n and n 1 are configured to capture rising edges ELS n B ELS n A 0 1 and ELS n 1 B ELS n 1 A 0 1 then the period between two consecutive rising edges is measured If both c...

Page 389: ...0 23 CH n 1 F bit CH n F bit clear CH n F 1 Problem 1 channel n input 0 set DECAP not clear CH n F and not clear CH n 1 F Problem 2 channel n input 1 set DECAP not clear CH n F and clear CH n 1 F Prob...

Page 390: ...1 13 15 6 8 10 12 16 14 24 22 20 18 26 25 21 Figure 12 257 Dual edge capture continuous mode to measure of the period between two consecutive rising edges 12 4 21 5 Read coherency mechanism The dual e...

Page 391: ...turns the FTM counter low byte value when the event 2 occurred and the read of C n 1 VH returns the FTM counter high byte value when the event 2 occurred channel n input after the filter C n VH L FTM...

Page 392: ...unter when MODH L 0x0000 or MODH L 0xFFFF If FTMEN 1 then the FTM counter is a free running counter when CPWMS 0 CNTINH L 0x0000 and MODH L 0xFFFF 12 4 22 3 Write to SC If FTMEN 0 then a write to the...

Page 393: ...put Note Do not use the above cases together with fault control Fault control If fault control is enabled and the fault condition is at the enabled fault input these cases reset the FTM counter to the...

Page 394: ...rolled only by FTM when CLKS 1 0 bits are different from zero table Mode Edge and Level Selection 1 FTM reset 0x0016 0x0015 0x0014 0x0013 0x0011 0x0010 0x0018 0x0017 XXXX 0x0000 0x0012 FTM counter CLK...

Page 395: ...0014 0b00 XX 0b01 4 use of initialization to update the channel output to the zero Figure 12 260 FTM behavior after the reset when the channel n is in output compare mode FTM Interrupts 12 6 1 Timer o...

Page 396: ...FTM Interrupts MC9S08PT60 Reference Manual Rev 4 08 2014 396 Freescale Semiconductor Inc...

Page 397: ...up counter Free running or 8 bit modulo limit Software controllable interrupt on overflow Counter reset bit TRST Counter stop bit TSTP Four software selectable clock sources for input to prescaler Sys...

Page 398: ...h an interrupt the MTIM continues from the state it was in when stop3 was entered If the counter was active upon entering stop3 the count will resume from the current value 13 3 3 MTIM in active backg...

Page 399: ...neral purpose port pin 13 6 Register definition MTIM memory map Absolute address hex Register name Width in bits Access Reset value Section page 18 MTIM Status and Control Register MTIM0_SC 8 R W 10h...

Page 400: ...modulo register 6 TOIE MTIM Overflow Interrupt Enable This read write bit enables MTIM overflow interrupts If TOIE is set then an interrupt is generated when TOF 1 Reset clears TOIE Do not set TOIE i...

Page 401: ...1 Encoding 1 Fixed frequency clock XCLK 10 Encoding 2 External source TCLK pin falling edge 11 Encoding 3 External source TCLK pin rising edge PS Clock Source Prescaler These four read write bits sele...

Page 402: ...Bit 7 6 5 4 3 2 1 0 Read MOD Write Reset 0 0 0 0 0 0 0 0 MTIMx_MOD field descriptions Field Description MOD MTIM Modulo These eight read write bits contain the modulo value used to reset the count and...

Page 403: ...e prescaler select bits CLK PS in MTIM_CLK select the desired prescale value If the counter is active SC TSTP 0 when a new prescaler value is selected the counter will continue counting from the previ...

Page 404: ..._CNT MTIM clock PS 0010 MTIM_MOD 0xA7 0xA8 0xA9 0xAA 0x00 0x01 0xAA Figure 13 14 MTIM counter overflow example In the above example the selected clock source could be any of the four possible choices...

Page 405: ...ns It can also serve as a cyclic wake up from low power modes Stop3 and Wait without the need of external components 14 2 Features Features of the RTC module include 16 bit up counter 16 bit modulo ma...

Page 406: ...t of stop modes with no external components if the real time interrupt is enabled 14 2 2 Block diagram The block diagram for the RTC module is shown in the following figure CLOCK DIVIDER BUS CLK RTCLK...

Page 407: ...flag RTIF and the toggle output enable bit RTCO Address 306Ah base 0h offset 306Ah Bit 7 6 5 4 3 2 1 0 Read RTIF RTIE 0 RTCO 0 Write Reset 0 0 0 0 0 0 0 0 RTC_SC1 field descriptions Field Description...

Page 408: ...1h offset 306Bh Bit 7 6 5 4 3 2 1 0 Read RTCLKS 0 RTCPS Write Reset 0 0 0 0 0 0 0 0 RTC_SC2 field descriptions Field Description 7 6 RTCLKS Real Time Clock Source Select These two read write bits sel...

Page 409: ...0 0 0 0 0 0 0 RTC_MODH field descriptions Field Description MODH RTC Modulo High These sixteen read write bits MODH and MODL contain the modulo value used to reset the count to 0x0000 upon a compare...

Page 410: ...ounter and then read RTC_CNTH to correctly read 16 bit counter Address 306Ah base 4h offset 306Eh Bit 7 6 5 4 3 2 1 0 Read CNTH Write Reset 0 0 0 0 0 0 0 0 RTC_CNTH field descriptions Field Descriptio...

Page 411: ...XOSC on chip low power oscillator LPO and bus clock The RTC Clock Select field RTC_SC2 RTCLKS is used to select the desired clock source to the prescaler dividers If a different value is written to RT...

Page 412: ...RTC_SC2 RTCPS is selected nonzero The RTC allows for an interrupt to be generated whenever RTC_SC1 RTIF is set To enable the real time interrupt set the Real Time Interrupt Enable field RTC_SC1 RTIE...

Page 413: ...cted The prescaler is set to RTC_SC2 RTCPS 001b or passthrough The actual modulo value used by 16 bit comparator is 32767 when the modulo value in the RTC_MODH and RTC_MODL registers is set to 32766 W...

Page 414: ...terrupt every 1 second from XOSC 32 768KHz clock source RTC_MOD 511 overflow every 32 times RTC_SC2 RTC_SC2_RTCPS_MASK external 32768 clock selected with 1 64 predivider RTC_SC1 RTC_SC1_RTIF_MASK RTC_...

Page 415: ...noise error Idle receiver detect Active edge on receive pin Break detect supporting LIN Hardware parity generation and checking Programmable 8 bit or 9 bit character length Programmable 1 bit or 2 bit...

Page 416: ...nsmit Control Shift Enable SCI Controls TxD Loop Control To Receive Data In Tx Interrupt Request TXDIR Load From SCIxD TXINV BRK13 LOOPS RSRC TIE TC TDRE PT PE TCIE TE SBK T8 Pin Logic TO TxD TxD Dire...

Page 417: ...akeup Logic All 1s From Transmitter Error Interrupt Request Parity Checking Divide By 16 Active Edge Detect RXINV LBKDE RWUID From RxD Pin msb RDRF RIE IDLE ILIE OR ORIE FE FEIE NF NEIE PF PEIE PT PE...

Page 418: ...tate meaning Whether TxD is interpreted as a 1 or 0 depends on the bit encoding method along with other configuration settings Timing Driven at the beginning or within a bit time according to the bit...

Page 419: ...gister 3 SCI1_C3 8 R W 00h 15 3 7 427 308F SCI Data Register SCI1_D 8 R W 00h 15 3 8 428 3090 SCI Baud Rate Register High SCI2_BDH 8 R W 00h 15 3 1 419 3091 SCI Baud Rate Register Low SCI2_BDL 8 R W 0...

Page 420: ...2 SCI Baud Rate Register Low SCIx_BDL This register along with SCI_BDH control the prescale divisor for SCI baud rate generation To update the 13 bit baud rate setting SBR12 SBR0 first write to SCI_B...

Page 421: ...S bit is set to 1 When LOOPS is set the receiver input is internally connected to the TxD pin and RSRC determines whether this connection is also connected to the transmitter output 0 Provided LOOPS i...

Page 422: ...ddress Base address 3h offset Bit 7 6 5 4 3 2 1 0 Read TIE TCIE RIE ILIE TE RE RWU SBK Write Reset 0 0 0 0 0 0 0 0 SCIx_C2 field descriptions Field Description 7 TIE Transmit Interrupt Enable for TDRE...

Page 423: ...eup condition The wakeup condition is an idle line between messages WAKE 0 idle line wakeup or a logic 1 in the most significant data bit in a character WAKE 1 address mark wakeup Application software...

Page 424: ...acter is all 1s these bit times and the stop bits time count toward the full character time of logic high 10 or 11 bit times depending on the M control bit needed for the receiver to detect an idle li...

Page 425: ...Register 2 SCIx_S2 This register contains one read only status flag When using an internal oscillator in a LIN system it is necessary to raise the break detection threshold one bit time Under the wors...

Page 426: ...Length BRK13 selects a longer transmitted break character length Detection of a framing error is not affected by the state of this bit 0 Break character is transmitted with length of 10 bit times if M...

Page 427: ...o change in the new value such as when it is used to generate mark or space parity it need not be written each time SCI_D is written 5 TXDIR TxD Pin Direction in Single Wire Mode When the SCI is confi...

Page 428: ...register are also involved in the automatic flag clearing mechanisms for the SCI status flags Address Base address 7h offset Bit 7 6 5 4 3 2 1 0 Read R7T7 R6T6 R5T5 R4T4 R3T3 R2T2 R1T1 R0T0 Write Rese...

Page 429: ...Sampling Clock 16 Baud Rate Tx Baud Rate Divide By 16 SCI Module Clock SCI Module Clock Figure 15 35 SCI baud rate generation SCI communications require the transmitter and receiver which typically d...

Page 430: ...trol bit and SCI_BDH SBNS bit For the remainder of this section assume SCI_C1 M is cleared SCI_BDH SBNS is also cleared selecting the normal 8 bit data mode In 8 bit data mode the shift register holds...

Page 431: ...g receivers Normally a program would wait for SCI_S1 TDRE to become set to indicate the last character of a message has moved to the transmit shifter then write 0 and then write 1 to the SCI_C2 TE bit...

Page 432: ...ects that the receive data register is full SCI_S1 RDRF 1 it gets the data from the receive data register by reading SCI_D The SCI_S1 RDRF flag is cleared automatically by a two step sequence normally...

Page 433: ...Receiver wake up operation Receiver wake up is a hardware mechanism that allows an SCI receiver to ignore the characters in a message intended for a different SCI receiver In such a system all receive...

Page 434: ...b be reserved for use in address frames The one or two if SCI_BDH SBNS 1 logic 1s msb of an address frame clears the SCI_C2 RWU bit before the stop bits are received and sets the SCI_S1 RDRF flag In t...

Page 435: ...at prevents it from getting set repeatedly when the RxD line remains idle for an extended period of time IDLE is cleared by reading SCI_S1 while SCI_S1 IDLE is set and then reading SCI_D After SCI_S1...

Page 436: ...A SAMPLES RECEIVER RT CLOCK STOP Figure 15 36 Slow data For an 8 bit data and 1 stop bit character data sampling of the stop bit takes the receiver 9 bit times x 16 RT cycles 10 RT cycles 154 RT cycle...

Page 437: ...8 bit data and 1 stop bit character data sampling of the stop bit takes the receiver 9 bit times x 16 RT cycles 10 RT cycles 154 RT cycles With the misaligned character shown in Figure 15 37 the rece...

Page 438: ...transmit data buffer this bit is stored in T8 in SCI_C3 For the receiver the ninth bit is held in SCI_C3 R8 For coherent writes to the transmit data buffer write to SCI_C3 T8 before writing to SCI_D...

Page 439: ...to the receiver causes the receiver to receive characters that are sent out by the transmitter 15 4 6 4 Single wire operation When SCI_C1 LOOPS is set SCI_C1 RSRC chooses between loop mode SCI_C1 RSR...

Page 440: ...Functional description MC9S08PT60 Reference Manual Rev 4 08 2014 440 Freescale Semiconductor Inc...

Page 441: ...divided by four in slave mode Software can poll the status flags or SPI operation can be interrupt driven NOTE For the actual maximum SPI baud rate refer to the Chip Configuration details and to the...

Page 442: ...s synchronized to the master Stop Mode To reduce power consumption the SPI is inactive in stop modes where the peripheral bus clock is stopped but internal logic states are retained If the SPI is conf...

Page 443: ...1 SPI System Connections 16 1 3 2 SPI Module Block Diagram The following is a block diagram of the SPI module The central element of the SPI is the SPI shift register Data is written to the double buf...

Page 444: ...SELECT CLOCK LOGIC MODE FAULT DETECTION 8 BIT COMPARA SPIxMR MASTER SLAVE SPSCK SS S M S M S M MOSI MOMI MISO SISO INTERRUPT REQUEST SPE LSBFE MSTR SPMF SPMIE SPTIE SPIE MODF SPRF SPTEF MOD SSOE SPC0...

Page 445: ...0 not bidirectional mode this pin is the serial data input When the SPI is enabled as a slave and SPC0 is 0 this pin is the serial data output If SPC0 is 1 to select single wire bidirectional mode an...

Page 446: ...includes the SPI enable control interrupt enables and configuration options Address 3098h base 0h offset 3098h Bit 7 6 5 4 3 2 1 0 Read SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE Write Reset 0 0 0 0 0 1...

Page 447: ...ts for details 0 First edge on SPSCK occurs at the middle of the first cycle of a data transfer 1 First edge on SPSCK occurs at the start of the first cycle of a data transfer 1 SSOE Slave select outp...

Page 448: ...e description of the SSOE bit in the C1 register 0 Mode fault function disabled master SS pin reverts to general purpose I O not controlled by SPI 1 Mode fault function enabled master SS pin acts as t...

Page 449: ...Address 3098h base 2h offset 309Ah Bit 7 6 5 4 3 2 1 0 Read 0 SPPR 2 0 SPR 3 0 Write Reset 0 0 0 0 0 0 0 0 SPI0_BR field descriptions Field Description 7 Reserved This field is reserved This read onl...

Page 450: ...base 3h offset 309Bh Bit 7 6 5 4 3 2 1 0 Read SPRF SPMF SPTEF MODF 0 Write Reset 0 0 1 0 0 0 0 0 SPI0_S field descriptions Field Description 7 SPRF SPI read buffer full flag SPRF is set at the comple...

Page 451: ...ly when MSTR is 1 MODFEN is 1 and SSOE is 0 otherwise MODF will never be set MODF is cleared by reading MODF while it is 1 and then writing to the SPI control register 1 C1 0 No mode fault error 1 Mod...

Page 452: ...7h offset 309Fh Bit 7 6 5 4 3 2 1 0 Read Bits 7 0 Write Reset 0 0 0 0 0 0 0 0 SPI0_M field descriptions Field Description Bits 7 0 Hardware compare value low byte 16 4 Functional Description This sec...

Page 453: ...when the MSTR bit is clear slave mode is selected 16 4 2 Master Mode The SPI operates in master mode when the MSTR bit is set Only a master SPI module can initiate transmissions A transmission begins...

Page 454: ...en an SPI interrupt sequence is also requested When a write to the SPI Data Register in the master occurs there is a half SPSCK cycle delay After the delay SPSCK is started within the master The rest...

Page 455: ...rmation from all of the receiving slaves If the CPHA bit in SPI Control Register 1 is clear odd numbered edges on the SPSCK input cause the data at the serial data input pin to be latched Even numbere...

Page 456: ...LSB first lines show the order of SPI data bits depending on the setting in LSBFE Both variations of SPSCK polarity are shown but only one of these waveforms applies for a specific transfer depending...

Page 457: ...r MISO and MOSI inputs respectively At the third SPSCK edge the SPI shifter shifts one bit position which shifts in the bit value that was just sampled and shifts the second data bit value out the oth...

Page 458: ...f a master The MOSI waveform applies to the MOSI output pin from a master and the MISO waveform applies to the MISO output from a slave The SS OUT waveform applies to the slave select output from a ma...

Page 459: ...4 5 6 7 or 8 The three rate select bits SPR3 SPR2 SPR1 SPR0 divide the output of the prescaler stage by 2 4 8 16 32 64 128 256 or 512 to get the internal SPI master mode bit rate clock The baud rate g...

Page 460: ...this mode the SPI uses only one serial data pin for the interface with one or more external devices The MSTR bit decides which pin to use The MOSI pin becomes the serial data I O MOMI pin for the mas...

Page 461: ...F bit in the SPI status register automatically provided that the MODFEN bit is set In the special case where the SPI is in master mode and the MODFEN bit is cleared the SS pin is not used by the SPI I...

Page 462: ...module enters a power conservation state when the CPU is in wait mode If SPISWAI is set and the SPI is configured for master any transmission and reception in progress stops at wait mode entry The tr...

Page 463: ...o this type of stop mode the SPI module clock is disabled held high or low If the SPI is in master mode and exchanging data when the CPU enters the stop mode the transmission is frozen until the CPU e...

Page 464: ...rmine which event caused the interrupt The service routine should also clear the flag bit s before returning from the ISR usually near the beginning of the ISR 16 4 10 1 MODF MODF occurs when the mast...

Page 465: ...terrupt enables This register also sets the SPI as master or slave determines clock phase and polarity and configures the main SPI options 2 Update control register 2 SPIx_C2 to enable additional SPI...

Page 466: ...unction when mode fault enabled Bit 0 LSBFE 0 SPI serial data transfers start with most significant bit SPIx_C2 0x80 10000000 Bit 7 SPMIE 1 SPI hardware match interrupt enabled Bit 6 0 Unimplemented B...

Page 467: ...UE READ SPMF WHILE SET TO CLEAR FLAG THEN WRITE A 1 TO IT YES SPMF 1 NO NO NO YES YES YES READ WRITE TO SPRF 1 SPTEF 1 INITIALIZE SPI SPIx_C1 0x54 SPIx_C2 SPIx_BR 0x00 0x80 SPIx_D SPIx_D Figure 16 18...

Page 468: ...Initialization Application Information MC9S08PT60 Reference Manual Rev 4 08 2014 468 Freescale Semiconductor Inc...

Page 469: ...runs at a baud rate up to the bus clock divided by two in master mode and up to the bus clock divided by four in slave mode Software can poll the status flags or SPI operation can be interrupt driven...

Page 470: ...clear the SPI operates like in Run mode If C2 SPISWAI is set the SPI goes into a power conservative state with the SPI clock generation turned off If the SPI is configured as a master any transmissio...

Page 471: ...vice initiates all SPI data transfers During a transfer the master shifts data out on the MOSI pin to the slave while simultaneously shifting data in on the MISO pin from the slave The transfer effect...

Page 472: ...CPU interrupts to occur when transmitting receiving high volume high speed data When FIFO mode is enabled the SPI can still function in either 8 bit or 16 bit mode as per SPIMODE bit and three additi...

Page 473: ...ROE IN FIFOMODE Rx FIFO 64 bits deep Tx BUFFER EMPTY Rx BUFFER FULL SHIFT CLOCK Tx FIFO 64 bits deep 8 OR 16 BIT MODE SPIMODE RNFULLF RNFULLIEN TNEAREF TNEARIEN MH ML Figure 17 2 SPI Module Block Diag...

Page 474: ...l zero SPC0 is 0 not bidirectional mode this pin is the serial data input When the SPI is enabled as a slave and SPC0 is 0 this pin is the serial data output If SPC0 is 1 to select single wire bidirec...

Page 475: ...r low SPI1_ML 8 R W 00h 17 3 8 484 8 30A8 SPI control register 3 SPI1_C3 8 R W 00h 17 3 9 485 9 30A9 SPI clear interrupt register SPI1_CI 8 R W 00h 17 3 10 486 17 3 1 SPI Control Register 1 SPIx_C1 Th...

Page 476: ...terrupts from SPTEF inhibited use polling 1 When SPTEF is 1 hardware interrupt requested 4 MSTR Master Slave Mode Select Selects master or slave mode operation 0 SPI module configured as a slave SPI d...

Page 477: ...offset 30A1h Bit 7 6 5 4 3 2 1 0 Read SPMIE SPIMODE Reserved MODFEN BIDIROE Reserved SPISWAI SPC0 Write Reset 0 0 0 0 0 0 0 0 SPI1_C2 field descriptions Field Description 7 SPMIE SPI Match Interrupt E...

Page 478: ...his field is reserved Do not write to this reserved bit 1 SPISWAI SPI Stop in Wait Mode This bit is used for power conservation while the device is in Wait mode 0 SPI clocks continue to operate in Wai...

Page 479: ...n for details 0000 Baud rate divisor is 2 0001 Baud rate divisor is 4 0010 Baud rate divisor is 8 0011 Baud rate divisor is 16 0100 Baud rate divisor is 32 0101 Baud rate divisor is 64 0110 Baud rate...

Page 480: ...ported or not enabled FIFOMODE is not present or is 0 SPRF is set at the completion of an SPI transfer to indicate that received data may be read from the SPI data DH DL register SPRF is cleared by re...

Page 481: ...omatically moves to the shifter and SPTEF will be set only when all data written to the transmit FIFO has been transfered to the shifter If no new data is waiting in the transmit FIFO SPTEF simply rem...

Page 482: ...O empty flag This bit indicates the status of the read FIFO when FIFOMODE is enabled If FIFOMODE is not enabled ignore this bit NOTE At an initial POR the values of TNEAREF and RFIFOEF are 0 However t...

Page 483: ...new data is lost because the receive buffer still held the previous character and was not ready to accept the new data There is no indication for a receive overrun condition so the application system...

Page 484: ...ly the ML register is available Reads of the MH register return all zeros Writes to the MH register are ignored In 16 bit mode reading either byte the MH or ML register latches the contents of both by...

Page 485: ...ed on the watermark feature of the TNEARF and RNFULLF flags of the S register Address 30A0h base 8h offset 30A8h Bit 7 6 5 4 3 2 1 0 Read 0 TNEAREF_ MARK RNFULLF_ MARK INTCLR TNEARIEN RNFULLIEN FIFOMO...

Page 486: ...e in the receive data buffer 17 3 10 SPI clear interrupt register SPIx_CI This register applies only for an instance of the SPI module that supports the FIFO feature The register has four bits dedicat...

Page 487: ...ed 1 Transmit FIFO overflow condition occurred 4 RXFOF Receive FIFO overflow flag This flag indicates that a receive FIFO overflow condition has occurred 0 Receive FIFO overflow condition has not occu...

Page 488: ...rted or inverted clock C1 CPHA is used to accommodate two fundamentally different protocols by sampling data on odd numbered SPSCK edges or on even numbered SPSCK edges The SPI can be configured to op...

Page 489: ...ress when the mode fault occurs the transmission is aborted and the SPI is forced into idle state This mode fault error also sets the Mode Fault MODF flag in the SPI Status Register SPIx_S If the SPI...

Page 490: ...vices there is no serial data out pin Note When peripherals with duplex capability are used take care not to simultaneously enable two receivers whose serial outputs drive the same system slave s seri...

Page 491: ...PC0 set C1 CPOL C1 CPHA C1 SSOE C1 LSBFE C2 MODFEN and C2 SPC0 in slave mode will corrupt a transmission in progress and must be avoided 17 4 4 SPI FIFO Mode When the FIFO feature is supported The SPI...

Page 492: ...here they remain latched until the other byte is read Writing to either byte SPIx_DH or SPIx_DL latches the value into a buffer When both bytes have been written they are transferred as a coherent 16...

Page 493: ...p of the figure the eight bit times are shown for reference with bit 1 starting at the first SPSCK edge and bit 8 ending one half SPSCK cycle after the eighth SPSCK edge The MSB first and LSB first li...

Page 494: ...t values on their MISO and MOSI inputs respectively At the third SPSCK edge the SPI shifter shifts one bit position which shifts in the bit value that was just sampled and shifts the second data bit v...

Page 495: ...he MOSI waveform applies to the MOSI output pin from a master and the MISO waveform applies to the MISO output from a slave The SS OUT waveform applies to the slave select output from a master provide...

Page 496: ...isor of 1 2 3 4 5 6 7 or 8 The three rate select bits SPR3 SPR2 SPR1 SPR0 divide the output of the prescaler stage by 2 4 8 16 32 64 128 256 or 512 to get the internal SPI master mode bit rate clock T...

Page 497: ...uses only one serial data pin for the interface with one or more external devices C1 MSTR decides which pin to use The MOSI pin becomes the serial data I O MOMI pin for the master mode and the MISO p...

Page 498: ...n and it sets the MODF bit in the SPI status register automatically provided that C2 MODFEN is set In the special case where the SPI is in master mode and C2 MODFEN is cleared the SS pin is not used b...

Page 499: ...wer conservation state when the CPU is in wait mode If C2 SPISWAI is set and the SPI is configured for master any transmission and reception in progress stops at Wait mode entry The transmission and r...

Page 500: ...ry to this type of stop mode the SPI module clock is disabled held high or low If the SPI is in master mode and exchanging data when the CPU enters the Stop mode the transmission is frozen until the C...

Page 501: ...routine ISR should check the flag bits to determine which event caused the interrupt The service routine should also clear the flag bit s before returning from the ISR usually near the beginning of th...

Page 502: ...F occurs when the data in the receive data buffer is equal to the data in the SPI Match Register In 8 bit mode SPMF is set only after bits 7 0 in the receive data buffer are determined to be equivalen...

Page 503: ...nal SPI functions such as the SPI match interrupt feature the master mode fault function and bidirectional mode output as well as to control 8 or 16 bit mode selection and other optional features 3 Up...

Page 504: ...0 SPI data I O pin acts as input Bit 2 0 Reserved Bit 1 SPISWAI 0 SPI clocks operate in wait mode Bit 0 SPC0 0 uses separate pins for data input and output SPIx_BR 0x00 00000000 Bit 7 0 Reserved Bit...

Page 505: ...uffer RESET CONTINUE READ SPMF WHILE SET TO CLEAR FLAG THEN WRITE A 1 TO IT YES SPMF 1 NO NO NO YES YES YES READ WRITE TO SPRF 1 SPTEF 1 INITIALIZE SPI SPIxC1 0x54 SPIxC2 SPIxBR 0x00 0xC0 SPIxMH 0xXX...

Page 506: ...t FIFOMODE TXFULLF 1 RNFULLF 1 SPRF 1 RFIFOEF 1 SPIxDH SPIxDL SPIxDH SPIxDL SPIxMH 0xXX Figure 17 29 Initialization Flowchart Example for SPI Master Device in 16 bit Mode for FIFOMODE 1 Initialization...

Page 507: ...n be connected are limited by a maximum bus capacitance of 400 pF The I2C module also complies with the System Management Bus SMBus Specification version 2 18 1 1 Features The I2C module has the follo...

Page 508: ...sic mode of operation To conserve power in this mode disable the module Wait mode The module continues to operate when the core is in Wait mode and can provide a wakeup interrupt Stop mode The module...

Page 509: ...igure 18 1 I2C Functional block diagram 18 2 I2C signal descriptions The signal properties of I2C are shown in the table found here Table 18 1 I2C signal descriptions Signal Description I O SCL Bidire...

Page 510: ...rol and Status register I2C_SMB 8 R W 00h 18 3 9 517 3079 I2C Address Register 2 I2C_A2 8 R W C2h 18 3 10 519 307A I2C SCL Low Timeout Register High I2C_SLTH 8 R W 00h 18 3 11 519 307B I2C SCL Low Tim...

Page 511: ...ing edge of SCL I2C clock to the changing of SDA I2C data SDA hold time I2C module clock period s mul SDA hold value The SCL start hold time is the delay from the falling edge of SDA I2C data while SC...

Page 512: ...ST is changed from 0 to 1 a START signal is generated on the bus and master mode is selected When this bit changes from 1 to 0 a STOP signal is generated and the mode of operation changes from master...

Page 513: ...ripheral bus running when slave address matching occurs 0 Normal operation No interrupt generated when address matching in low power mode 1 Enables the wakeup function in low power mode 0 Reserved Thi...

Page 514: ...RBL bit must be cleared by software by writing 1 to it 0 Standard bus operation 1 Loss of arbitration 3 RAM Range Address Match This bit is set to 1 by any of the following conditions if I2C_C2 RMEN 1...

Page 515: ...ading the Data register to prevent an inadvertent initiation of a master receive data transfer In slave mode the same functions are available after an address match occurs The C1 TX bit must correctly...

Page 516: ...esses between the values of the A1 and RA registers When this bit is set a slave address matching occurs for any address greater than the value of the A1 register and less than or equal to the value o...

Page 517: ...ption 7 1 RAD Range Slave Address This field contains the slave address to be used by the I2C module The field is used in the 7 bit address scheme If I2C_C2 RMEN is set to 1 any nonzero value write en...

Page 518: ...ut the device s address on the bus The alert protocol is described in the SMBus specification 0 SMBus alert response address matching is disabled 1 SMBus alert response address matching is enabled 5 S...

Page 519: ...ble Enables SCL high and SDA low timeout interrupt 0 SHTF2 interrupt is disabled 1 SHTF2 interrupt is enabled 18 3 10 I2C Address Register 2 I2C_A2 Address 3070h base 9h offset 3079h Bit 7 6 5 4 3 2 1...

Page 520: ...4 Functional description This section provides a comprehensive functional description of the I2C module 18 4 1 I2C protocol The I2C bus system uses a serial data line SDA and a serial clock line SCL f...

Page 521: ...evice is engaging the bus both SCL and SDA are high When the bus is free a master may initiate communication by sending a START signal A START signal is defined as a high to low transition of SDA whil...

Page 522: ...stable while SCL is high There is one clock pulse on SCL for each data bit and the MSB is transferred first Each data byte is followed by a ninth acknowledge bit which is signaled from the receiving d...

Page 523: ...ely switch to slave receive mode and stop driving SDA output In this case the transition from master to slave mode does not generate a STOP condition Meanwhile hardware sets a status bit to indicate t...

Page 524: ...low a slave can drive SCL low for the required period and then release it If the slave s SCL low period is greater than the master s SCL low period the resulting SCL bus signal s low period is stretch...

Page 525: ...6 97 286 289 0D 48 11 20 25 2D 640 97 318 321 0E 56 13 24 29 2E 768 129 382 385 0F 68 13 30 35 2F 960 129 478 481 10 48 9 18 25 30 640 65 318 321 11 56 9 22 29 31 768 65 382 385 12 64 13 26 33 32 896...

Page 526: ...st 7 bits 11110 AD10 AD9 R W 0 A1 Slave address second byte AD 8 1 A2 Data A Data A A P After the master transmitter has sent the first byte of the 10 bit address the slave receiver sees an I2C interr...

Page 527: ...ing process It provides a 7 bit address If the ADEXT bit is set AD 10 8 in Control Register 2 participates in the address matching process It extends the I2C primary slave address to a 10 bit address...

Page 528: ...on and be able to receive a new START condition within the timeframe of TTIMEOUT MAX SMBus defines a clock low timeout TTIMEOUT of 35 ms specifies TLOW SEXT as the cumulative clock low extend time for...

Page 529: ...out intervals TLOW SEXT and TLOW MEXT When in master mode the I2C module must not cumulatively extend its clock cycles for a period greater than TLOW MEXT within a byte where each byte is defined as S...

Page 530: ...to acknowledge its own address as a mechanism to detect the presence of a removable device such as a battery or docking station on the bus In addition to indicating a slave device busy condition SMBu...

Page 531: ...CIF IICIE Match of received calling address IAAS IICIF IICIE Arbitration lost ARBL IICIF IICIE SMBus SCL low timeout SLTF IICIF IICIE SMBus SCL high SDA low timeout SHTF2 IICIF IICIE SHTF2IE Wakeup fr...

Page 532: ...ss or data transmit cycle 2 SDA is sampled as low when the master drives high during the acknowledge bit of a data receive cycle 3 A START cycle is attempted when the bus is busy 4 A repeated START cy...

Page 533: ...internal signals DFF DFF DFF Figure 18 17 Programmable input glitch filter diagram 18 4 8 Address matching wake up When a primary range or general call address match occurs when the I2C module is in...

Page 534: ...ransmit data 4 Initialize RAM variables used to achieve the routine shown in the following figure 5 Write Control Register 1 to enable TX 6 Write Control Register 1 to enable MST master mode 7 Write D...

Page 535: ...Notes 1 If general call is enabled check to determine if the received address is a general call address 0x00 If the received address is a general call address the general call must be handled by user...

Page 536: ...a to Data reg Clear IICIF Notes 1 If general call or SIICAEN is enabled check to determine if the received address is a general call address 0x00 or an SMBus device default address In either case they...

Page 537: ...s Output formatted in 8 10 or 12 bit right justified unsigned format Single or Continuous Conversion automatic return to idle after single conversion Support up to eight result FIFO with selectable FI...

Page 538: ...Input Channel FIFO Fulfilled AD0 AD1 AD2 AD14 AD15 AD16 AD21 AD20 AD22 AD23 AD29 AD30 AD31 AD32 Compare Value 2 ANALOG MUX CLK MUX AD CHANNEL FIFO AD RESULT FIFO 12 bit AD result 12 bit AD result 12...

Page 539: ...o VSS If externally available connect the VSSA pin to the same voltage potential as VSS 19 2 3 Voltage Reference High VREFH VREFH is the high reference voltage for the converter In some packages VREFH...

Page 540: ...ister ADC_APCTL1 8 R W 00h 19 3 9 548 30AD Pin Control 2 Register ADC_APCTL2 8 R W 00h 19 3 10 549 19 3 1 Status and Control Register 1 ADC_SC1 This section describes the function of the ADC status an...

Page 541: ...uous Conversion Enable ADCO enables continuous conversions 0 One conversion following a write to the ADC_SC1 when software triggered operation is selected or one conversion following assertion of ADHW...

Page 542: ...ger is selected a conversion is initiated following the assertion of the ADHWT input 0 Software trigger selected 1 Hardware trigger selected 5 ACFE Compare Function Enable Enables the compare function...

Page 543: ...The power is reduced at the expense of maximum clock speed 6 5 ADIV Clock Divide Select ADIV selects the divide ratio used by the ADC to generate the internal clock ADCK 00 Divide ration 1 and clock...

Page 544: ...ways use the first dummied FIFO channels when it is enabled When this bit is set and FIFO function is enabled ADC will repeat using the first FIFO channel as the conversion channel until the result FI...

Page 545: ...111 8 level FIFO is enabled 19 3 5 Conversion Result High Register ADC_RH In 12 bit operation ADC_RH contains the upper four bits of the result of a 12 bit conversion ADC_RH is updated each time a con...

Page 546: ...read If ADC_RL is not read until the next conversion is completed the intermediate conversion results are lost In 8 bit mode there is no interlocking with ADC_RH If the MODE bits are changed any data...

Page 547: ...4 Reserved This field is reserved This read only field is reserved and always has the value 0 CV Conversion Result 15 8 19 3 8 Compare Value Low Register ADC_CVL This register holds the lower 8 bits o...

Page 548: ...he pin associated with channel AD6 0 AD6 pin I O control enabled 1 AD6 pin I O control disabled 5 ADPC5 ADC Pin Control 5 ADPC5 controls the pin associated with channel AD5 0 AD5 pin I O control enabl...

Page 549: ...Write Reset 0 0 0 0 0 0 0 0 ADC_APCTL2 field descriptions Field Description 7 ADPC15 ADC Pin Control 15 ADPC15 controls the pin associated with channel AD15 0 AD15 pin I O control enabled 1 AD15 pin I...

Page 550: ...bits are all high The module is idle when a conversion has completed and another conversion has not been initiated When idle the module is in its lowest power state The ADC can perform an analog to d...

Page 551: ...s a maximum divide by 16 of the bus clock ALTCLK that is alternate clock which is OSCOUT The asynchronous clock ADACK This clock is generated from a clock source within the ADC module When selected as...

Page 552: ...er function operates in conjunction with any of the conversion modes and configurations 19 4 4 Conversion control Conversions can be performed in 12 bit mode 10 bit mode or 8 bit mode as determined by...

Page 553: ...tion false blocking has no effect and ADC operation is terminated In all other cases of operation when a data transfer is blocked another conversion is initiated regardless of the state of ADC_SC1 ADC...

Page 554: ...rsion time depends on the sample time as determined by ADC_SC3 ADLSMP the MCU bus frequency the conversion mode 8 bit 10 bit or 12 bit and the frequency of the conversion clock fADCK After the module...

Page 555: ...nt continuous 8 bit fBUS fADCK xx 0 17 ADCK cycles Subsequent continuous 10 bit or 12 bit fBUS fADCK xx 0 20 ADCK cycles Subsequent continuous 8 bit fBUS fADCK 11 xx 1 37 ADCK cycles Subsequent contin...

Page 556: ..._SC4 ACFSEL is low or if not all of compare conditions are true when ADC_SC4 ACFSEL is high ADC_SC1 COCO is not set The compare data are transferred to the result registers regardless of compare condi...

Page 557: ...O complete whatever software or hardware trigger is set An interrupt request will be submitted to CPU if the ADC_SC1 AIEN is set when the FIFO conversion completes and the ADC_SC1 COCO bit is set AD C...

Page 558: ...C stops conversions when ADC_SC1 COCO bit is set until the channel FIFO is fulfilled again or new hardware trigger occur The FIFO also provides scan mode to simplify the dummy work of input channel FI...

Page 559: ...ware Triggered Continuous Conversion COCO 1 Conversions Completed max Only need one hardware trigger If new trigger occurs the new set conversions will be generated max AFDEP max 0 n max AFDEP 0 n max...

Page 560: ...sabled 19 4 8 1 Stop3 mode with ADACK disabled If the asynchronous clock ADACK is not selected as the conversion clock executing a STOP instruction aborts the current conversion and places the ADC in...

Page 561: ...ersion and a polled or interrupt approach among many other options Refer to ADC_SC3 register for information used in this example Note Hexadecimal values prefixed by a 0x binary values prefixed by a a...

Page 562: ..._SC1 ADC_SC1_AIEN_MASK ADC_SC1_ADCH0_MASK 19 5 2 ADC FIFO module initialization example Before the ADC module can be used to start FIFOed conversions an initialization procedure must be performed A ty...

Page 563: ...dware trigger ADC_SC2 ADC_SC2_ADTRG_MASK 4 Level FIFO ADC_SC4 ADC_SC4_AFDEP1_MASK ADC_SC4_AFDEP0_MASK dummy the 1st channel ADC_SC1 ADC_SC1_ADCH0_MASK dummy the 2nd channel ADC_SC1 ADC_SC1_ADCH1_MASK...

Page 564: ...VSSA and VDDA are shared with the MCU digital supply pins In these cases there are separate pads for the analog supplies bonded to the same pin as the corresponding digital supply so that some degree...

Page 565: ...um parasitic only 19 6 1 3 Analog input pins The external analog inputs are typically shared with digital I O pins on MCU devices The pin I O control is disabled by setting the appropriate control bit...

Page 566: ...oximately 5 5 pF sampling to within 1 4 LSB at 12 bit resolution can be achieved within the minimum sample window 3 5 cycles at 8 MHz maximum ADCK frequency provided the resistance of the external ana...

Page 567: ...put on the MCU during the conversion There are some situations where external system activity causes radiated or conducted noise emissions or excessive VDD noise is coupled into the ADC In these situa...

Page 568: ...is 1 lsb to 0 lsb and the code width of each step is 1 lsb 19 6 2 5 Linearity errors The ADC may also exhibit non linearity of several forms Every effort has been made to reduce these errors but the...

Page 569: ...y when the input voltage is infinitesimally smaller than the transition voltage the converter yields the lower code and vice versa However even small amounts of system noise can cause the converter to...

Page 570: ...Application information MC9S08PT60 Reference Manual Rev 4 08 2014 570 Freescale Semiconductor Inc...

Page 571: ...applications where voltage reference is needed The 64 tap resistor ladder network divides the supply reference Vin into 64 voltage level A 6 bit digital signal input selects output voltage level which...

Page 572: ...ake the MCU up from Stop3 mode If the Stop3 is exited by an interrupt the ACMP setting remains before entering the Stop mode If Stop3 is exited with a reset the ACMP goes into its reset The user must...

Page 573: ...external pin ACMP_CS ACOPE controls the pin to enable disable the ACMP output function 20 3 Memory map and register definition ACMP memory map Absolute address hex Register name Width in bits Access...

Page 574: ...1 to this bit has no effect 4 ACIE ACMP Interrupt Enable Enables an ACMP CPU interrupt 0 Disable the ACMP Interrupt 1 Enable the ACMP Interrupt 3 ACO ACMP Output Reading ACO will return the current va...

Page 575: ...ved and always has the value 0 5 4 ACPSEL ACMP Positive Input Select 00 External reference 0 01 External reference 1 10 Reserved 11 DAC output 3 2 Reserved This field is reserved This read only field...

Page 576: ...n 7 3 Reserved This field is reserved This read only field is reserved and always has the value 0 ACIPE ACMP Input Pin Enable This 3 bit field controls if the corresponding ACMP external pin can be dr...

Page 577: ...ling edge on ACMP output is valid When ACMP_CS ACMOD 01b only rising edge on ACMP output is valid When ACMP_CS ACMOD 11b both the rising edge and falling edge on the ACMP output are valid The ACMP out...

Page 578: ...ring a reset the ACMP is configured in the default mode Both CMP and DAC are disabled 20 7 Interrupts If the bus clock is available when a valid edge defined in ACMP_CS ACMOD occurs the ACMP_CS ACF is...

Page 579: ...id capacitive measurement module to the implementation of touch keyboard rotaries and sliders 21 1 1 Features TSI features includes Support up to 16 external electrodes Automatic detection of electrod...

Page 580: ...functional in this mode When a scan completes TSI submits an interrupt request to CPU if the interrupt is enabled 21 1 3 Block diagram The following figure is a block diagram of the TSI module ANALOG...

Page 581: ...duce distribution capacity on board 21 3 Register definition This section describes the memory map and control status registers for the TSI module TSI memory map Absolute address hex Register name Wid...

Page 582: ...3 mode if this interrupt is enabled 0 TSI interrupt disabled 1 TSI interrupt enabled 5 STPE STPE This bit enables TSI module function in stop3 mode When this bit is set TSI can be woken by external ha...

Page 583: ...swapped 1 The current source pair are swapped 0 SWTS SWTS This write only bit is a software start trigger When STM bit is clear write 1 to this bit will start a scan The electrode channel to be scanne...

Page 584: ...es per electrode 01000 9 times per electrode 01001 10 times per electrode 01010 11 times per electrode 01011 12 times per electrode 01100 13 times per electrode 01101 14 times per electrode 01110 15 t...

Page 585: ...A 011 4 A 100 8 A 101 16 A 110 32 A 111 64 A 4 3 DVOLT DVOLT These bits indicate the oscillator s voltage rails as below 00 V 1 03 V VP 1 33 V Vm 0 30 V 01 V 0 73 V VP 1 18 V Vm 0 45 V 10 V 0 43 V VP...

Page 586: ...Channel 10 1011 Channel 11 1100 Channel 12 1101 Channel 13 1110 Channel 14 1111 Channel 15 STAT_STUP STAT STU These bits are written as STUP and read as STAT for analog configuration and status detec...

Page 587: ...6 is enabled 5 PEN5 PEN5 This bit enables the touch sensing input pin 0 PEN5 is disabled 1 PEN5 is enabled 4 PEN4 PEN4 This bit enables the touch sensing input pin 0 PEN4 is disabled 1 PEN4 is enabled...

Page 588: ...Description 7 PEN15 PEN15 This bit enables the touch sensing input pin 0 PEN15 is disabled 1 PEN15 is enabled 6 PEN14 PEN14 This bit enables the touch sensing input pin 0 PEN14 is disabled 1 PEN14 is...

Page 589: ...EN8 is disabled 1 PEN8 is enabled 21 3 7 TSI Counter Register High TSI_CNTH Address 8h base 6h offset Eh Bit 7 6 5 4 3 2 1 0 Read CNTH Write Reset 0 0 0 0 0 0 0 0 TSI_CNTH field descriptions Field Des...

Page 590: ...21 4 1 1 TSI electrode oscillator The TSI electrode oscillator circuit is illustrated in the following figure A configurable constant current source is used to charge and discharge the external elect...

Page 591: ...ent source of I 16 A and V 1 03 V have the following oscillation frequency Felec 16 A 2 20pF 1 03V 0 39MHz Figure 21 12 TSI electrode oscillator frequency The current source is used to accommodate the...

Page 592: ...ave the following sampling time Tcap_samp 2 2 16 20pF 1 03V 16 A 82 4 s 21 4 1 3 TSI reference oscillator The TSI reference oscillator has the same topology of the TSI electrode oscillator The TSI ref...

Page 593: ...ap_samp Fref_osc Using Equation 2 and Equation 1 follows TSICHnCNT Iref PS NSCN Cref Ielec Celec Equation 4 Capacitance result value In the example where Fref_osc 7 8 MHz and Tcap_samp 82 4 s TSICHnCN...

Page 594: ...21 4 6 Clock setting TSI is built with dual oscillator architecture In normal sensing application the reference oscillator clock is the only clock source for operations The reference clock is used to...

Page 595: ...h can be used to charge a big electrode by less power consumption TSI_CS0 CURSW allows the current source to swap so that the reference oscillator and electrode oscillator use the opposite current sou...

Page 596: ...e circuit configuration as shown in the following figure With this configuration it is possible to detect touch with high levels of EMC noise present To enter this mode set TSI_CS3 STAT_STUP field to...

Page 597: ...aler counter2 clk en clk_ext clk_ref Cref REFCHRG EXTCHRG DVOLT 1pF PS NSCN Filter Filter STAT 1 0 STAT 1 0 Noise Mode Ref OSC Ref OSC Ext OSC 16 bit counter1 Count_noise TSI_CNTH TSI_CNTL Figure 21 1...

Page 598: ...n order To determine the noise level the TSI noise detection algorithm shall be performed by scanning this table following the arrow direction starting at maximum Rs and minimum DVOLT Rs Bits k DVOLT...

Page 599: ...d WINDOW is 2 This results in Tmin 20 s 4 Start TSI scan with software trigger or hardware trigger just as does for normal function mode 5 Wait until TSI scan is complete TSI_CS0 EOSF 1 6 Read TSI cou...

Page 600: ...level is found That is the correct TSI_CS2 DVOLT value and TSI_CS2 EXTCHRG value are found for the current noise level And now users can proceed with normal capacitive sense procedure by keeping both...

Page 601: ...a noise source external to the MCU It is possible to observe in the following figure that in noise detection mode the clkref output has the peak detection and the number of detected peaks can be coun...

Page 602: ...EXTCHRG 2 EXTCHRG 1 EXTCHRG 3 Figure 21 17 TSI noise detection mode waveform Functional description MC9S08PT60 Reference Manual Rev 4 08 2014 602 Freescale Semiconductor Inc...

Page 603: ...bit or 32 bit CRC standard These parameters are detailed in further sections 22 2 Features Features of the CRC module are Hardware 16 32 bit CRC generator Programmable initial seed value Programmable...

Page 604: ...tions in progress stop and will resume after the CPU goes into run mode 22 5 Register definition CRC memory map Absolute address hex Register name Width in bits Access Reset value Section page 3060 CR...

Page 605: ...1 1 1 1 1 CRC_D0 field descriptions Field Description DH0 CRC Data Bit 31 24 22 5 2 CRC Data 1 Register CRC_D1 D1 is one of the CRC data registers D0 D3 The set of CRC data registers contains the val...

Page 606: ...computation in which D0 D2 does not accept any data and D3 accept 8 bit write upon the polynomial configuration When final data are written the final result can be read from the data register The regi...

Page 607: ...mmy data to CRC Writing D2 will be ignored when WAS 0 Address 3060h base 3h offset 3063h Bit 7 6 5 4 3 2 1 0 Read D3 Write Reset 1 1 1 1 1 1 1 1 CRC_D3 field descriptions Field Description D3 CRC Data...

Page 608: ...ptions Field Description P1 CRC Polynominal Bit 23 16 22 5 7 CRC Polynomial 2 Register CRC_P2 P2 is one of the CRC polynomial registers P0 P3 The set of CRC polynominal registers contains the value of...

Page 609: ...ription P3 CRC Polynominal Bit 7 0 22 5 9 CRC Control Register CRC_CTRL Address 3060h base 8h offset 3068h Bit 7 6 5 4 3 2 1 0 Read TOT TOTR 0 FXOR WAS TCRC Write Reset 0 0 0 0 0 0 0 0 CRC_CTRL field...

Page 610: ...Generator 22 6 Functional description 22 6 1 16 bit CRC calculation The following steps show how to start a general 16 bit CRC calculation 1 Clear CRC_CTRL TCRC bit to enable 16 bit CRC mode 2 Optiona...

Page 611: ...lowing table shows how the CRC_CTRL TOT and CRC_CTRL TOTR bits work Table 22 11 TOT and TOTR bit and byte reverse function TOT ROW D0 D1 D2 D3 00 b31b30b29b28b27b26b 25b24 b23b22b21b20b19b18b 17b16 b1...

Page 612: ...1 Standard CCITT polynomail of x 16 x 12 x 5 1 CRC_D2D3 0xFFFF Set seed by 0xFFFF CRC_CTRL 0x00 for i 0 i 128 i CRC_D3 A Dummy 256 A CRC_D3 A Get 0xea0b in CRC_D2 CRC_D3 here Functional description MC...

Page 613: ...res Features of the WDOG module include Configurable clock source inputs independent from the bus clock Internal 32 kHz RC oscillator Internal 1 kHz RC oscillator External clock source Programmable ti...

Page 614: ...owing updates to write once configuration bits Software must make updates within 128 bus clocks after unlocking and before WDOG closing unlock window 23 1 2 Block diagram The following figure provides...

Page 615: ...ntrol and Status Register 1 WDOG_CS1 This section describes the function of Watchdog Control and Status Register 1 NOTE TST is cleared 0 0 on POR only Any other reset does not affect the value of this...

Page 616: ...alue of this field 00 Watchdog test mode disabled 01 Watchdog user mode enabled Watchdog test mode disabled After testing the watchdog software should use this setting to indicate that the watchdog is...

Page 617: ...urred 1 An interrupt occurred 5 Reserved This field is reserved This read only field is reserved and always has the value 0 4 PRES Watchdog Prescalar This write once bit enables a fixed 256 pre scalin...

Page 618: ...on 2 The unlock sequence allows the watchdog to be reconfigured without forcing a reset when WDOG_CS1 UPDATE 1 See the Example code Reconfiguring the Watchdog section NOTE All other writes to these re...

Page 619: ...reaches the timeout value the watchdog forces a reset NOTE Do not write 0 to the Watchdog Timeout Value Register otherwise the watchdog always generates a reset Address 3030h base 4h offset 3034h Bit...

Page 620: ...WINH and WDOG_WINL must be less than WDOG_TOVALH and WDOG_TOVALL Address 3030h base 6h offset 3036h Bit 7 6 5 4 3 2 1 0 Read WINHIGH Write Reset 0 0 0 0 0 0 0 0 WDOG_WINH field descriptions Field Desc...

Page 621: ...rogrammable but must be configured within 128 bus clocks after a reset 23 3 1 Watchdog refresh mechanism The watchdog resets the MCU if the watchdog counter is not refreshed A robust refresh mechanism...

Page 622: ...early When Window mode is enabled the watchdog must be refreshed after the counter has reached a minimum expected time value otherwise the watchdog resets the MCU The minimum expected time value is sp...

Page 623: ...out value and window value are write once after reset This means that after a write has occurred they cannot be changed unless a reset occurs This provides a robust mechanism to configure the watchdog...

Page 624: ...g within 128 bus clocks otherwise the watchdog forces a reset to the MCU NOTE Due to 128 bus clocks requirement for reconfiguring the watchdog some delays must be inserted before executing STOP or WAI...

Page 625: ...izes the different watchdog timeout periods available Table 23 10 Watchdog timeout availability Reference clock Prescaler Watchdog time out availability Internal 1 kHz LPO Pass through 1 ms 65 5 s1 25...

Page 626: ...ase the main WDOG logic loses its clock the bus clock and can no longer monitor the counter If the watchdog counter overflows twice in succession without an intervening reset the backup reset function...

Page 627: ...on from the low byte to the high byte is tested Using this test feature reduces the test time to 512 clocks not including overhead such as user configuration and reset vector fetches To further speed...

Page 628: ...Entering user mode After successfully testing the low and high bytes of the watchdog counter the user can configure WDOG_CS1 TST to 01b to indicate the watchdog is ready for use in application user mo...

Page 629: ...round command that writes a one to the BDFR bit in the SBDFR register Other causes of reset including an external pin reset or an internally generated error reset ignore the state of the BKGD pin and...

Page 630: ...pports in circuit programming of on chip nonvolatile memory and sophisticated non intrusive debug capabilities Unlike debug interfaces on earlier 8 bit MCUs this system does not interfere with normal...

Page 631: ...BKGD pin description BKGD is the single wire background debug interface pin The primary function of this pin is for bidirectional serial communication of active background mode commands and data Durin...

Page 632: ...ternal controller or by the MCU Data is transferred MSB first at 16 BDC clock cycles per bit nominal speed The interface times out if 512 BDC clock cycles occur between falling edges from the host Any...

Page 633: ...rated falling edge on BKGD to the perceived start of the bit time in the target MCU The host holds the BKGD pin low long enough for the target to recognize it at least two target BDC cycles The host m...

Page 634: ...E SPEED U P PU LSE EAR LIEST STAR T O F NEXT BIT H O ST SAM PLES BKG D PIN Figure 24 4 BDM target to host serial bit timing logic 0 24 2 3 BDC commands BDC commands are sent serially from a host compu...

Page 635: ...ol Refer to Freescale document order no HCS08RMv1 D ACK_DISABLE Non intrusive D6 d Disable acknowledge protocol Refer to Freescale document order no HCS08RMv1 D BACKGROUND Non intrusive 90 d Enter act...

Page 636: ...X WRITE_SP Active BDM 4F WD16 d Write stack pointer SP WRITE_NEXT Active BDM 50 WD d Increment H X by one then write memory byte located at H X WRITE_NEXT_WS Active BDM 51 WD d SS Increment H X by one...

Page 637: ...tagged breakpoint causes the instruction opcode at the breakpoint address to be tagged so that the CPU will enter active background mode rather than executing that instruction if and when it reaches...

Page 638: ...ress is actually executed as opposed to only being read from memory into the instruction queue The comparators are also capable of magnitude comparisons to support the inside range and outside range t...

Page 639: ...e FIFO by simply reading DBGFL Each time DBGFL is read the FIFO is shifted so the next data value is available through the FIFO data port at DBGFL In trigger modes where the FIFO is storing change of...

Page 640: ...change of flow from a jump branch subroutine call or interrupt causes some instructions that have been fetched into the instruction queue to be thrown away without being executed A force type breakpoi...

Page 641: ...ger modes and all such debug runs are begin type traces When TRGSEL 1 to select opcode fetch triggers it is not necessary to use R W in comparisons because opcode tags would apply only to opcode fetch...

Page 642: ...the address matches the value in comparator B Trigger events cause the data to be captured into the FIFO The debug run ends when the FIFO becomes full A Then Event Only B Store Data After the address...

Page 643: ...quate or header file is used to translate these names into the appropriate absolute addresses BDC memory map Absolute address hex Register name Width in bits Access Reset value Section page 0 BDC Stat...

Page 644: ...KPT match register When FTS 0 a match between the CPU address bus and the BDCBKPT register causes the fetched opcode to be tagged If this tagged opcode ever reaches the end of the instruction queue th...

Page 645: ...ecause the CPU entered wait or stop mode 0 DVF Data Valid Failure Status 0 Memory access did not conflict with a slow memory access 1 Memory access command failed because CPU was not finished with a s...

Page 646: ...1 0 Read A 7 0 Write Reset 0 0 0 0 0 0 0 0 BDC_BKPTL field descriptions Field Description A 7 0 Low 8 bit of hardware breakpoint address 24 4 4 System Background Debug Force Reset Register BDC_SBDFR...

Page 647: ...ode command such as WRITE_BYTE allows an external debug host to force a target system reset Writing 1 to this bit forces an MCU reset This bit cannot be written from a user program Chapter 24 Developm...

Page 648: ...Memory map and register description MC9S08PT60 Reference Manual Rev 4 08 2014 648 Freescale Semiconductor Inc...

Page 649: ...A B and C with ability to match addresses in 64 KB space Dual mode Comparators A and B used to compare addresses Full mode Comparator A compares address and Comparator B compares data Can be used as t...

Page 650: ...modes Ability to End trace until reset and begin trace from reset 25 1 2 Modes of operation The on chip ICE system can be enabled in all MCU functional modes The DBG module is disabled if the MCU is...

Page 651: ...ta Bus Trigger Break Control Logic c o n t r o FIFO Data DBG Read Data Bus DBG Module Enable addr 16 0 1 m u x Write Data Bus Read Data Bus Read Write l Comparator C match_C MCU reset core_cof 1 0 Rea...

Page 652: ...or B Extension Register DBG_CBX 8 R W 00h 25 3 10 659 301A Debug Comparator C Extension Register DBG_CCX 8 R W 00h 25 3 11 660 301B Debug FIFO Extended Information Register DBG_FX 8 R 00h 25 3 12 661...

Page 653: ...s are undefined in end run reset In the case of an end trace to reset where DBGEN 1 and BEGIN 0 the bits in this register do not change after reset Address 3010h base 1h offset 3011h Bit 7 6 5 4 3 2 1...

Page 654: ...bits control whether Comparator B will compare the address bus bits 15 8 to a logic 1 or logic 0 Not used in full mode 0 Compare corresponding address bit to a logic 0 1 Compare corresponding address...

Page 655: ...n end run reset In the case of an end trace to reset where DBGEN 1 and BEGIN 0 the bits in this register do not change after reset Address 3010h base 4h offset 3014h Bit 7 6 5 4 3 2 1 0 Read CC 15 8 W...

Page 656: ...ompare bits control whether Comparator C will compare the address bus bits 7 0 to a logic 1 or logic 0 0 Compare corresponding address bit to a logic 0 1 Compare corresponding address bit to a logic 1...

Page 657: ...is register do not change after reset Address 3010h base 7h offset 3017h Bit 7 6 5 4 3 2 1 0 Read F 7 0 Write Reset 0 0 0 0 0 0 0 0 DBG_FL field descriptions Field Description F 7 0 FIFO Low Data Bits...

Page 658: ...escription 7 RWAEN Read Write Comparator A Enable Bit The RWAEN bit controls whether read or write comparison is enabled for Comparator A 0 Read Write is not used in comparison 1 Read Write is used in...

Page 659: ...ad or write comparison is enabled for Comparator B In full modes RWAEN and RWA are used to control comparison of R W and RWBEN is ignored 0 Read Write is not used in comparison 1 Read Write is used in...

Page 660: ...Description 7 RWCEN Read Write Comparator C Enable Bit The RWCEN bit controls whether read or write comparison is enabled for Comparator C 0 Read Write is not used in comparison 1 Read Write is used i...

Page 661: ...y the internal signal mmu_ppage_sel which is 1 when the access is through the PPAGE mechanism 0 The information in the corresponding FIFO word is event only data or an unpaged 17 bit CPU address with...

Page 662: ...erved This read only field is reserved and always has the value 0 0 LOOP1 Select LOOP1 Capture Mode This bit selects either normal capture mode or LOOP1 capture mode LOOP1 is not used in event only mo...

Page 663: ...nd Trigger Bit The BEGIN bit controls whether the trigger begins or ends storing of data in FIFO 0 Trigger at end of stored data 1 Trigger before storing data 5 4 Reserved This field is reserved This...

Page 664: ...ator A did not match 1 Comparator A match 6 BF Trigger B Match Bit The BF bit indicates if Trigger B match condition was met since arming 0 Comparator B did not match 1 Comparator B match 5 CF Trigger...

Page 665: ...20 shows the correlation between the CNT bits and the amount of valid data in FIFO The CNT will stop after a count to eight even if more data is being stored in the FIFO The CNT bits are cleared when...

Page 666: ...l TBC block 25 4 1 1 RWA and RWAEN in full modes In full modes A And B and A And Not B DBG_CAX RWAEN and DBG_CAX RWA are used to select read or write comparisons for both comparators A and B To select...

Page 667: ...r B are desired set DBG_T BEGIN 0 to select an end trace run and set the trigger mode to either 0x0 A only or 0x1 A OR B mode There are two types of breakpoint requests supported by the DBG module tag...

Page 668: ...ontroller for the DBG module Its function is to decide whether data should be stored in the FIFO based on the trigger mode and the match signals from the comparator The TBC also determines whether a r...

Page 669: ...RKEN 1 is triggered when the FIFO becomes full Since this FIFO full condition does not correspond to the execution of a tagged instruction it would not make sense to use DBG_C TAG 1 for a begin type t...

Page 670: ...corresponding flag s in the DBG_S register are set 25 4 4 3 3 A then B In the A then B trigger mode the match condition for A must be met before the match condition for B is compared When the match co...

Page 671: ...rigger mode if the match condition for A and not B happen on the same bus cycle both the DBG_S AF and DBG_S BF flags are set If a match condition on only A or only not B occur no flags are set For bre...

Page 672: ...dress then force CPU breakpoint 0 0 1 1 Do not use 0 1 0 x Fill FIFO until trigger opcode about to execute no CPU breakpoint keep running 0 1 1 0 0 1 1 1 Fill FIFO until trigger opcode about to execut...

Page 673: ...n the begin trigger mode data is not stored in the FIFO until the trigger condition is met Once the trigger condition is met the DBG module will remain armed until 8 words are stored in the FIFO If th...

Page 674: ...led profile mode 25 4 6 Interrupt priority When DBG_T TRGSEL is set and the DBG module is armed to trigger on begin or end trigger types a trigger is not detected in the condition where a pending inte...

Page 675: ...ost DBG control and status bits is overridden so a host development system can read out the results of the trace run after the MCU has been reset In all other cases including POR the DBG module contro...

Page 676: ...Resets MC9S08PT60 Reference Manual Rev 4 08 2014 676 Freescale Semiconductor Inc...

Page 677: ...e Initialization application information Serial communications interface SCI Corrected SCI receiver block diagram in the Block diagram Added SCI signal descriptions Added a note to the Transmitter fun...

Page 678: ...in Enable TSI module Updated the examples in the TSI electrode oscillator Electrode oscillator and counter module control TSI reference oscillator and TSI measurement result Updated the table of the...

Page 679: ...ims any and all liability including without limitation consequential or incidental damages Typical parameters that may be provided in Freescale data sheets and or specifications can and do vary in dif...

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