Freescale Semiconductor MC9S08PT60, Reference Manual

Page: 517 / 679

I2C_FLT field descriptions
Field Description
7
Reserved
This field is reserved.
Writing this bit has no effect.
6–5
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
FLT I2C Programmable Filter Factor
Controls the width of the glitch, in terms of I2C module clock cycles, that the filter must absorb. For any
glitch whose size is less than or equal to this width setting, the filter does not allow the glitch to pass.
00h No filter/bypass
01-1Fh Filter glitches up to width of n I2C module clock cycles, where n =1-31d
18.3.8 I2C Range Address register (I2C_RA)
Address: 3070h base + 7h offset = 3077h
Bit 7 6 5 4 3 2 1 0
Read
RAD
0
Write
Reset
0 0 0 0 0 0 0 0
I2C_RA field descriptions
Field Description
7–1
RAD
Range Slave Address
This field contains the slave address to be used by the I2C module. The field is used in the 7-bit address
scheme. If I2C_C2[RMEN] is set to 1, any nonzero value write enables this register. This register value
can be considered as a maximum boundary in the range matching mode.
0
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
18.3.9 I2C SMBus Control and Status register (I2C_SMB)
NOTE
When the SCL and SDA signals are held high for a length of
time greater than the high timeout period, the SHTF1 flag sets.
Before reaching this threshold, while the system is detecting
how long these signals are being held high, a master assumes
that the bus is free. However, the SHTF1 bit is set to 1 in the
bus transmission process with the idle bus state.
Chapter 18 Inter-Integrated Circuit (I2C)
MC9S08PT60 Reference Manual, Rev. 4, 08/2014
Freescale Semiconductor, Inc. 517