HOST INTERFACE (HI)
MOTOROLA
PORT B
5 - 61
the HI.
5. The DMA controller latches the data presented on H0-H7 and deasserts
HACK. If the byte register read was not RXL (i.e., not $7), the HI’s internal
DMA counter increments, and HREQ is again asserted. Steps 3, 4, and 5 are
repeated until RXL is read.
6. If RXL was read, RXDF will be set to zero and, since HTDE=0, the contents of
HTX will be automatically transferred to RXH:RXM:RXL, and RXFD will be set
to one. Steps 3, 4, and 5 are repeated until RXL is read again.
Note:
The transfer of data from the HTX register to the RXH:RXM:RXL registers auto-
matically loads the DMA address counter from the HM1 and HM0 bits when in the
DMA DSP–HOST mode. This DMA address is used within the HI to place the ap-
propriate byte on H0-H7.
5.3.6.3.4
DSP to Host DMA Procedure
The following procedure outlines the typical steps that the host processor must take to
setup and terminate a DSP-to-host DMA transfer (see Figure 5-40).
1. Set up the DMA controller (1) destination address, byte count, direction, and
other control registers. Enable the DMA controller channel.
2. Initialize the HI (2) by writing the ICR to select the word size (HM0 and HM1),
the direction (TREQ=0, RREQ=1), and setting INIT=1 (see Figure 5-40 for
additional information on these bits).
3. Initialize the DSP’s source pointer (3) used in the DMA exception handler (an
address register, for example), and set HTIE to enable the DSP host transmit
interrupt. This could be done by the host processor with a host command
exception routine.
The DSP host transmit exception will be activated immediately after HTIE is
set. The DSP CPU will move data to HTX. The HI circuitry will transfer the con-
tents of HTX to RXH:RXM:RXL, setting RXDF which asserts HREQ. Asserting
HREQ (4) starts the DMA transfer from RXH, RXM, and RXL to the host pro-
cessor.
4. Perform other tasks (5) while the DMA controller transfers data (6) until inter-
rupted by the DMA controller DMA complete interrupt (7). The DSP interrupt
control register (ICR), the interrupt status register (ISR), and TXH, TXM, and
TXL may be accessed at any time by the host processor but the RXH, RXM
and RXL registers may not be accessed until the DMA mode is disabled.
5. Terminate the DMA controller channel (8) to disable DMA transfers.
6. Terminate the DSP HI DMA mode (9) in the Interrupt Control Register (ICR) by
clearing the HM1 and HM0 bits and clearing RREQ.
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Freescale Semiconductor, Inc.
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