TIMER/EVENT COUNTER MODULE PIN
2 - 14
DSP56002 PIN DESCRIPTIONS
MOTOROLA
•
Output Clock (CKOUT) — This output pin provides a 50% duty cycle output
clock synchronized to the internal processor clock when the PLL is enabled and
locked. When the PLL is disabled, the output clock at CKOUT is derived from,
and has the same frequency and duty cycle as, EXTAL.
Note: If the PLL is enabled and the multiplication factor is less than or equal to
4, then CKOUT is synchronized to EXTAL. (For information on the
DSP56002’s PLL multiplication factor, see Section Section 3.6 PLL
MULTIPLICATION FACTOR.
•
CKOUT Polarity Control (CKP) — This input pin defines the polarity of the CK-
OUT clock output. Strapping CKP through a resistor to GND will make the CK-
OUT polarity the same as the EXTAL polarity. Strapping CKP through a resistor
to Vcc will make the CKOUT polarity the inverse of the EXTAL polarity. The CK-
OUT clock polarity is internally latched at the end of the hardware reset, so that
any changes of the CKP pin logic state after deassertion of hardware reset will
not affect the CKOUT clock polarity.
•
PLL Initialization Input (PINIT) — During the assertion of hardware reset, the
value at the PINIT input pin is written into the PEN bit of the PLL control register.
The PEN bit enables the PLL by causing it to derive the internal clocks from the
PLL VCO output. When the bit is clear, the PLL is disabled and the chip’s inter-
nal clocks are derived from the clock connected to the EXTAL pin. After hard-
ware reset is deasserted, the PINIT pin is ignored.
•
Phase and Frequency Locked (PLOCK) — The PLOCK output originates
from the Phase Detector. The chip asserts PLOCK when the PLL is enabled
and has locked on the proper phase and frequency of EXTAL. The PLOCK out-
put is deasserted by the chip if the PLL is enabled and has not locked on the
proper phase and frequency. PLOCK is asserted if the PLL is disabled. PLOCK
is a reliable indicator of the PLL lock state only after the chip has exited the
hardware reset state. During hardware reset, the PLOCK state is determined
by PINIT and by the PLL lock condition.
2.5
TIMER/EVENT COUNTER MODULE PIN
The bidirectional TIO pin is the pin that provides an interface to the timer/event counter mod-
ule. When the TIO is used as an input, the module functions as an external event counter,
or it measures external pulse width/signal period. When the TIO is used as an output, the
module functions as a timer and the signal on the TIO pin is the timer pulse. When the timer
module is not using the TIO pin, the TIO can act as a general purpose I/O pin.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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