HOST INTERFACE (HI)
MOTOROLA
PORT B
5 - 17
5.3.2.2.6
HSR Reserved Status (Bits 5 and 6)
These status bits are reserved for future expansion and read as zero during DSP
read operations.
5.3.2.2.7
HSR DMA Status (DMA) Bit 7
The DMA bit indicates that the host processor has enabled the DMA mode of the HI by
setting HM1 or HM0 to one. When the DMA bit is zero, it indicates that the DMA mode is
disabled by the HM0 and HM1 bits in the ICR and that no DMA operations are pending.
When the DMA bit is set, the DMA mode has been enabled if one or more of the host
mode bits have been set to one. The channel not in use can be used for polled or inter-
rupt operation by the DSP. Hardware, software, individual, and STOP resets clear the
DMA bit.
5.3.2.3
Host Receive Data Register (HRX)
The HRX register is used for host-to-DSP data transfers. The HRX register is viewed as
a 24-bit read-only register by the DSP CPU. The HRX register is loaded with 24-bit data
from the transmit data registers (TXH:TXM:TXL) on the host processor side when both
the transmit data register empty TXDE (host processor side) and DSP host receive data
full (HRDF) bits are cleared. This transfer operation sets TXDE and HRDF. The HRX reg-
ister contains valid data when the HRDF bit is set. Reading HRX clears HRDF. The DSP
may program the HRIE bit to cause a host receive data interrupt when HRDF is set.
Resets do not affect HRX.
5.3.2.4
Host Transmit Data Register (HTX)
The HTX register is used for DSP-to-host data transfers. The HTX register is viewed as a
24-bit write-only register by the DSP CPU. Writing the HTX register clears HTDE. The
DSP may program the HTIE bit to cause a host transmit data interrupt when HTDE is set.
The HTX register is transferred as 24-bit data to the receive byte registers
(RXH:RXM:RXL) if both the HTDE bit (DSP CPU side) and receive data full (RXDF) status
bits (host processor side) are cleared. This transfer operation sets RXDF and HTDE. Data
should not be written to the HTX until HTDE is set to prevent the previous data from being
overwritten. Resets do not affect HTX.
5.3.2.5
Register Contents After Reset
Table 5-1 shows the results of four reset types on bits in each of the HI registers seen by
the DSP CPU. The hardware reset (HW) is caused by the RESET signal; the software
reset (SW) is caused by executing the RESET instruction; the individual reset (IR) is
caused by clearing PBC register bits 0 and 1, and the stop reset (ST) is caused by exe-
cuting the STOP instruction.
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Freescale Semiconductor, Inc.
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