SYNCHRONOUS SERIAL INTERFACE (SSI)
6 - 88
PORT C
MOTOROLA
These bits control the number of active clock transitions in the gated clock modes and
control the word length divider (see Figure 6-42 and Figure 6-43), which is part of the
frame rate signal generator for continuous clock modes. The WL control bits also control
the frame sync pulse length when FSL0 and FSL1 select a WL bit clock (see Figure 6-42).
Hardware and software reset clear WL0 and WL1.
6.4.2.1.4
CRA Prescaler Range (PSR) Bit 15
The PSR controls a fixed divide-by-eight prescaler in series with the variable prescaler.
This bit is used to extend the range of the prescaler for those cases where a slower bit
clock is desired (see Figure 6-42). When PSR is cleared, the fixed prescaler is bypassed.
When PSR is set, the fixed divide-by-eight prescaler is operational. This allows a 128-kHz
master clock to be generated for MC14550x series codecs.
The maximum internally generated bit clock frequency is fosc/4, the minimum internally
generated bit clock frequency is fosc/4/8/256=fosc/8192. Hardware and software reset
clear PSR.
6.4.2.2
SSI Control Register B (CRB)
The CRB is one of two 16-bit read/write control registers used to direct the operation of
the SSI. CRB controls the SSI multifunction pins, SC2, SC1, and SC0, which can be used
as clock inputs or outputs, frame synchronization pins, or serial I/O flag pins. The serial
output flag control bits and the direction control bits for the serial control pins are in the
SSI CRB. Interrupt enable bits for each data register interrupt are provided in this control
register. When read by the DSP, CRB appears on the two low-order bytes of the 24-bit
word, and the high-order byte reads as zeros. Operating modes are also selected in this
register. Hardware and software reset clear all the bits in the CRB. The relationships be-
tween the SSI pins (SC0, SC1, SC2, and SCK) and some of the CRB bits are summarized
in Tables Table 6-5, Table 6-12, and Table 6-13. The SSI CRB bits are described in the
following paragraphs.
6.4.2.2.1
CRB Serial Output Flag 0 (OF0) Bit 0
When the SSI is in the synchronous clock mode and the serial control direction zero bit
(SCD0) is set, indicating that the SC0 pin is an output, then data present in OF0 will be
written to SC0 at the beginning of the frame in normal mode or at the beginning of the next
time slot in network mode. Hardware and software reset clear OF0.
6.4.2.2.2
CRB Serial Output Flag 1 (OF1) Bit 1
When the SSI is in the synchronous clock mode and the serial control direction one
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Freescale Semiconductor, Inc.
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