PORT A TIMING
4 - 10
PORT A
MOTOROLA
is equivalent to repeating the T2 and T2 clock phases. The write signal is also delayed
from the T1 to the T2 state when one or more wait states are added to ease interfacing to
the port. Each external memory access requires the following procedure:
1. The external memory address is defined by the address bus (A0–A15) and the
memory reference selects (PS, DS, and X/Y). These signals change in the first
phase (T0) of the bus cycle. Since the memory reference select signals have
the same timing as the address bus, they may be used as additional address
lines. The address and memory reference signals are also used to generate
chip-select signals for the appropriate memory chips. These chip-select sig-
nals change the memory chips from low-power standby mode to active mode
and begin the read access time. This mode change allows slower memories to
be used since the chip-select signals can be address based rather than read
or write enable based. Read and write enable do not become active until after
the address is valid. See the timing diagrams in the
DSP56002 Advance Infor-
mation Data Sheet (DSP56002/D
) for detailed timing information.
2. When the address and memory reference signals are stable, the data transfer
T0
T1
T2
TW
TW
TW
TW
T3
T0
T1
ONE CLOCK CYCLE
INTERNAL CLOCK PHASES
ADDRESS PS, DS, X/Y
A
B
C
RD
DATA IN
WR
DATA OUT
READ
CYCLE
WRITE
CYCLE
ONE INSTRUCTION CYCLE
TWO WAIT STATES
DATA LATCHED HERE
Figure 4-7 Port A Bus Operation with Two Wait States
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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