SERIAL COMMUNICATION INTERFACE (SCI)
MOTOROLA
PORT C
6 - 23
in addition, TDRE is set in the middle of transmitting the second bit. When using an exter-
nal serial transmit clock, if the clock stops, the SCI transmitter stops. TDRE will not be set
until the middle of the second bit transmitted after the external clock starts. Gating the ex-
ternal clock off after the first bit has been transmitted will delay TDRE indefinitely.
In the SCI asynchronous mode, the TDRE flag is not set immediately after a word is trans-
ferred from the STX or STXA to the transmit shift register nor when the word first begins
to be shifted out. TDRE is set two cycles of the 16
×
clock after the start bit – i.e., two 16
×
clock cycles into to transmission time of the first data bit.
6.3.2.2.3
SSR Receive Data Register Full (RDRF) Bit 2
The RDRF bit is set when a valid character is transferred to the SCI receive data register
from the SCI receive shift register. RDRF is cleared when the SCI receive data register is
read or by the hardware, software, SCI individual, and stop reset.
6.3.2.2.4
SSR Idle Line Flag (IDLE) Bit 3
IDLE is set when 10 (or 11) consecutive ones are received. IDLE is cleared by a start-bit
detection. The IDLE status bit represents the status of the receive line. The transition of
IDLE from zero to one can cause an IDLE interrupt (ILIE). IDLE is cleared by the hard-
ware, software, SCI individual, and stop reset.
6.3.2.2.5
SSR Overrun Error Flag (OR) Bit 4
The OR flag is set when a byte is ready to be transferred from the receive shift register to
the receive data register (SRX) that is already full (RDRF=1). The receive shift register
data is not transferred to the SRX. The OR flag indicates that character(s) in the receive
data stream may have been lost. The only valid data is located in the SRX. OR is cleared
when the SCI status register is read, followed by a read of SRX. The OR bit clears the FE
and PE bits – i.e., overrun error has higher priority than FE or PE. OR is cleared by the
hardware, software, SCI individual, and stop reset.
6.3.2.2.6
SSR Parity Error (PE) Bit 5
In the 11-bit asynchronous modes, the PE bit is set when an incorrect parity bit has been
detected in the received character. It is set simultaneously with RDRF for the byte which
contains the parity error – i.e., when the received word is transferred to the SRX. If PE is
set, it does not inhibit further data transfer into the SRX. PE is cleared when the SCI status
register is read, followed by a read of SRX. PE is also cleared by the hardware, software,
SCI individual, or stop reset. In the 10-bit asynchronous mode, the 11-bit multidrop mode,
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Freescale Semiconductor, Inc.
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