SERIAL COMMUNICATION INTERFACE (SCI)
MOTOROLA
PORT C
6 - 57
6.3.8.1
Transmitting Data and Address Characters
Transmitting data and address when the multidrop mode is selected is shown in Figure
6-30. The output sequence shown is idle line, data/address, and the next character. In
both cases, an “A” is being transmitted. To send data, TE must be toggled to send the idle
line, and then “A” must be sent to STX. Sending the “A” to the STX sets the ninth bit in the
frame to zero, which indicates that this frame contains data. If the “A” is sent to STXA in-
stead, the ninth bit in the frame is set to a one, which indicates that this frame contains an
address.
6.3.8.2
Wired-OR Mode
Building a multidrop bus network requires connecting multiple transmitters to a common
wire. The wired-OR mode allows this to be done without damaging the transmitters when
the transmitters are not in use. A protocol is still needed to prevent two transmitters from
simultaneously driving the bus. The SCI multidrop word format provides an address field
to support this protocol. Figure 6-31 shows a multidrop configuration using wired-OR (set
bit 7 of the SCR). The protocol shown consists of an idle line between messages; each
message begins with an address character. The message can be any length, depending
on the protocol. Each processor in this system has one address that it responds to al-
though each processor can be programmed to respond to more than one address.
6.3.8.3
Idle Line Wakeup
A wakeup mode frees a DSP from reading messages intended for other processors. The
usual operational procedure is for each DSP to suspend SCI reception (the DSP can con-
tinue processing) until the beginning of a message. Each DSP compares the address in
the message header with the DSPs address. If the addresses do not match, the SCI again
suspends reception until the next address. If the address matches, the DSP will read and
process the message and then suspend reception until the next address.
The idle line wakeup mode wakes up the SCI to read a message before the first character
arrives. This mode allows the message to be in any format.
Figure 6-32 shows how to configure the SCI to detect and respond to an idle line. The
word format chosen (WDS2, WDS1, and WDS0 in the SCR) must be asynchronous. The
WAKE bit must be clear to select idle line wakeup, and RWU must be set to put the SCI
to “sleep” and enable the wakeup function. RIE should be set if interrupts are to be used
to receive data. If processing must occur when the idle line is first detected, ILIE should
be set. The current message is followed by one or more data frames of ones (10 or 11 bits
each, depending on which word format is used), which are detected as an idle line. If the
word format is multidrop (an 11-bit code), after the 11 ones, the receiver determines the
line is idle and (1) clears the RWU, enabling the receiver. The IDLE bit (2) and an internal
flag SRIINT (3) are set, indicating the line is idle. The SCI is now ready to receive mes-
sages; however, nothing more will happen until the next start bit unless (4) ILIE is set.
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Freescale Semiconductor, Inc.
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