SYNCHRONOUS SERIAL INTERFACE (SSI)
MOTOROLA
PORT C
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of a frame sync.
6.4.2.2.14
CRB SSI Transmit Interrupt Enable (TIE) Bit 14
The DSP will be interrupted when TIE and the TDE flag in the SSI status register is set.
(In network mode, the interrupt takes effect in the next frame synch, not in the next time
slot.) When TIE is cleared, this interrupt is disabled. However, the TDE bit will always in-
dicate the transmit data register empty condition even when the transmitter is disabled
with the TE bit. Writing data to TX or TSR will clear TDE, thus clearing the interrupt. Hard-
ware and software reset clear RE.
There are two transmit data interrupts that have separate interrupt vectors:
1. Transmit data with exceptions – This interrupt is generated on the following
condition:
TIE=1, TDE=1, and TUE=1
2. Transmit data without exceptions – This interrupt is generated on the following
condition:
TIE=1, TDE=1, and TUE=0
See SECTION 7 PROCESSING STATES in the DSP56000 Family Manual for more in-
formation on exceptions.
6.4.2.2.15
CRB SSI Receive Interrupt Enable (RIE) Bit 15
When RIE is set, the DSP will be interrupted when RDF in the SSI status register is set.
(In network mode, the interrupt takes effect in the next frame synch, not in the next time
slot.) When RIE is cleared, this interrupt is disabled. However, the RDF bit still indicates
the receive data register full condition. Reading the receive data register will clear RDF,
thus clearing the pending interrupt. Hardware and software reset clear RIE.
There are two receive data interrupts that have separate interrupt vectors:
1. Receive data with exceptions – This interrupt is generated on the following
condition:
RIE=1, RDF=1, and ROE=1
2. Receive data without exceptions – This interrupt is generated on the following
condition:
RIE=1, RDF=1, and ROE=0
See SECTION 7 PROCESSING STATES in the DSP56000 Family Manual for more in-
formation on exceptions.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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