SYNCHRONOUS SERIAL INTERFACE (SSI)
MOTOROLA
PORT C
6 - 153
6.4.8
Flags
Two SSI pins (SC1 and SC0) are available in the synchronous mode for use as serial I/O
flags. The control bits (OF1 and OF0) and status bits (IF1 and IF0) are double buffered
to/from SC1 and SC0. Double buffering the flags keeps them in sync with TX and RX. The
direction of SC1 and SC0 is controlled by SCD1 and SCD0 in CRB.
Figure 6-87 shows the flag timing for a network mode example. Initially, neither TIE nor
TE is set, and the flag outputs are the last flag output value. When TIE is set, a TDE in-
terrupt occurs (the transmitter does not have to be enabled for this interrupt to occur).
Data (D1) is written to TX, which clears TDE, and the transmitter is enabled by software.
When the frame sync occurs, data (D1) is transferred to the transmit shift register, setting
TDE. Data (D1) is shifted out during the first word time, and the output flags are updated.
These flags will remain stable until the next frame sync. The TDE interrupt is then serviced
by writing data (D2) to TX, clearing TDE. After the TSR completes transmission, the trans-
mit pin is three-stated until the next frame sync
Figure 6-88 shows a speaker phone example that uses a DSP56002 and two codecs. No
additional logic is required to connect the codecs to the DSP. The two serial output flags
in this example (OF1 and OF0) are used as chip selects to enable the appropriate codec
for I/O. This procedure allows the transmit lines to be ORed together. The appropriate out-
put flag pin changes at the same time as the first bit of the transmit word and remains sta-
ble until the next transmit word (see Figure 6-89). Applications include serial-device chip
selects, implementing multidrop protocols, generating Bell PCM signaling frame syncs,
and outputting status information.
Initializing the flags (see Figure 6-89) is accomplished by setting SYN, SCD1, and SCD0.
No other control bits affect the flags. The synchronous control bit must be set (SYN=1) to
select the SC1 and SC0 pins as flags. SCD1 and SCD0 select whether SC1 and SC0 are
inputs or outputs (input=0, output=1). The other bits selected in Figure 6-89 are chosen
for the speaker phone example in Figure 6-88. In this example, the codecs require that
the SSI be set for normal mode (MOD=0) with a gated clock (GCK=1) out (SCKD=1).
Serial input flags, IF1 and IF0, are latched at the same time as the first bit is sampled in
the receive data word (see Figure 6-90). Since the input was latched, the signal on the
input flag pin can change without affecting the input flag until the first bit of the next receive
data word. To initialize SC1 or SC0 as input flags, the synchronous control bit in CRB
must be set to one (SYN=1) and SCD1 set to zero for pin SC1, and SCD0 must be set to
zero for pin SC0. The input flags are bits 1 and 0 in the SSISR (at X:$FFEE).
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Freescale Semiconductor, Inc.
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