HOST INTERFACE (HI)
5 - 30
PORT B
MOTOROLA
5.3.3.4.7
ISR DMA Status (DMA) Bit 6
The DMA status bit indicates that the host processor has enabled the DMA mode of the
HI (HM1 or HM0=1). When the DMA status bit is clear, it indicates that the DMA mode is
disabled (HM0=HM1=0) and no DMA operations are pending. When DMA is set, it indi-
cates that the DMA mode is enabled and the host processor should not use the active
DMA channel (RXH, RXM, RXL or TXH, TXM, TXL depending on DMA direction) to avoid
conflicts with the DMA data transfers. The channel not in use can be used for polled oper-
ation by the host and operates in the interrupt mode for internal DSP exceptions or poll-
ing. Hardware, software, individual, and STOP resets clear the DMA status bit.
5.3.3.4.8
ISR Host Request (HREQ) Bit 7
The HREQ bit indicates the status of the external host request output pin (HREQ). When
the HREQ status bit is cleared, it indicates that the external HREQ pin is deasserted and
no host processor interrupts or DMA transfers are being requested. When the HREQ sta-
tus bit is set, it indicates that the external HREQ pin is asserted, indicating that the DSP
is interrupting the host processor or that a DMA transfer request is occurring. The HREQ
interrupt request may originate from either or both of two sources – the receive byte reg-
isters are full or the transmit byte registers are empty. These conditions are indicated by
the ISR RXDF and TXDE status bits, respectively. If the interrupt source has been
enabled by the associated request enable bit in the ICR, HREQ will be set if one or more
of the two enabled interrupt sources is set. Hardware, software, individual, and STOP
resets clear HREQ.
5.3.3.5
Interrupt Vector Register (IVR)
The IVR is an 8-bit read/write register which typically contains the exception vector num-
ber used with MC68000 Family processor vectored interrupts. Only the host processor
can read and write this register. The contents of IVR are placed on the host data bus
(H0–H7) when both the HREQ and HACK pins are asserted and the DMA mode is dis-
abled. The contents of this register are initialized to $0F by a hardware or software reset,
which corresponds to the uninitialized exception vector in the MC68000 Family.
5.3.3.6
Receive Byte Registers (RXH, RXM, RXL)
The receive byte registers are viewed as three 8-bit read-only registers by the host pro-
cessor. These registers are called receive high (RXH), receive middle (RXM), and receive
low (RXL). These three registers receive data from the high byte, middle byte, and low
byte, respectively, of the HTX register and are selected by three external host address
inputs (HA2, HA1, and HA0) during a host processor read operation or by an on-chip
address counter in DMA operations. The receive byte registers (at least RXL) contain
valid data when the receive data register full (RXDF) bit is set. The host processor may
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