DSP56002 OPERATING MODES
3 - 10
MEMORY MODULES AND OPERATING MODES
MOTOROLA
After loading the internal memory, the DSP switches to the single-chip mode (Mode 0) and
begins program execution at on-chip program memory location $0000.
If the user selects Mode 1 through hardware (MODA, MODB, MODC pins), the following
actions occur once the processor comes out of the reset state.
1. The control logic maps the bootstrap ROM into the internal DSP program mem-
ory space starting at location $0000.
2. The control logic causes program reads to come from the bootstrap ROM (only
address bits 5–0 are significant) and all writes go to the program RAM (all ad-
dress bits are significant). This condition allows the bootstrap program to load
the user program from $0000–$01FF.
3. Program execution begins at location $0000 in the bootstrap ROM. The boot-
strap ROM program loads program RAM from the external byte-wide EPROM
starting at P:$C000.
4. The bootstrap ROM program ends the bootstrap operation and begins executing
the user program. The processor enters Mode 0 by writing to the OMR. This ac-
tion is timed to remove the bootstrap ROM from the program memory map and
re-enable read/write access to the program RAM. The change to Mode 0 is
timed to allow the bootstrap program to execute a single-cycle instruction (clear
status register), then a JMP #<00, and begin execution of the user program at
location $0000.
Address of External
Byte-Wide Memory
:
Contents Loaded to Internal
Program RAM at
:
P:$C000
P:$0000
low byte
P:$C001
P:$0000
mid byte
P:$C002
P:$0000
high byte
•
•
•
•
•
•
P:$C5FD
P:$01FF
low byte
P:$C5FE
P:$01FF
mid byte
P:$C5FF
P:$01FF
high byte
Table 3-3 Organization of EPROM Data Contents
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Freescale Semiconductor, Inc.
For More Information On This Product,
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