DSP56002 OPERATING MODES
3 - 8
MEMORY MODULES AND OPERATING MODES
MOTOROLA
Chip operating modes can also be changed using software to write the operating mode
bits (MC, MB, MA) in the OMR. Changing operating modes does not reset the DSP.
Note:
The user should disable interrupts immediately before changing the OMR to pre-
vent an interrupt from going to the wrong memory location. Also, one no-operation
(NOP) instruction should be included after changing the OMR to allow for remap-
ping to occur.
3.4.1
Single Chip Mode (Mode 0)
In the single-chip mode, all internal program and data RAM memories are enabled (see
Figure 3-1). A hardware reset causes the DSP to jump to internal program memory loca-
tion $0000 and resume execution. The memory maps for mode 0 and mode 2 (see Figure
3-1) are identical. The difference between the two modes is that reset vectors to program
memory location $0000 in mode 0 and vectors to location $E000 in mode 2.
3.4.2
Bootstrap From EPROM (Mode 1)
The bootstrap modes allow the DSP to load a program from an inexpensive byte-wide
ROM into internal program memory during a power-on reset. On power-up, the wait-
state generator adds 15 wait states to all external memory accesses so that slow mem-
ory can be used. The bootstrap program uses the bytes in three consecutive memory
locations in the external ROM to build a single word in internal program memory.
Operating
Mode
M
C
M
B
M
A
Description
0
0
0
0
Single-Chip Mode - P: RAM enabled, reset @ $0000
1
0
0
1
Bootstrap from EPROM, exit in Mode 0
2
0
1
0
Normal Expanded Mode - P: RAM enabled, reset @ $E000
3
0
1
1
Development Mode - P: RAM disabled, reset @ $0000
4
1
0
0
Reserved for Bootstrap
5
1
0
1
Bootstrap from Host, exit in Mode 0
6
1
1
0
Bootstrap from SCI (external clock), exit in Mode 0
7
1
1
1
Reserved for Bootstrap
Table 3-2 DSP56002 Operating Mode Summary
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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