DSP56002 INTERRUPT PRIORITY REGISTER
3 - 12
MEMORY MODULES AND OPERATING MODES
MOTOROLA
Note:
The difference between Modes 1 and 5 in the DSP56002 and Mode 1 in the
DSP56001 may be considered software incompatibility. A DSP56001 program that
reloads the internal P: RAM from the Host Port by setting MB-MA = 01 (assuming
external pull-up resistor on bit 23 of P:$C000) will not work correctly in the
DSP56002. In the DSP56002, the program would trigger a bootstrap from the exter-
nal EPROM. The solution is to modify the DSP56001 program to set MC-MA = 101.
3.4.7
Bootstrap From SCI (Mode 6)
In this mode, the Bootstrap ROM is enabled and the bootstrap program is executed. The
internal and/or external program RAM is loaded from the SCI serial interface. The number
of program words to load and the starting address must be specified. The SCI bootstrap
code expects to receive 3 bytes specifying the number of program words, 3 bytes speci-
fying the address from which to start loading the program words, and then 3 bytes for each
program word to be loaded. The number of words, the starting address and the program
words are received least significant byte first, followed by the mid-, and then by the most
significant byte. After receiving the program words, program execution starts at the ad-
dress where the first instruction was loaded. The SCI is programmed to work in
asynchronous mode with 8 data bits, 1 stop bit, and no parity. The clock source is external
and the clock frequency must be 16x the baud rate. After each byte is received, it is ech-
oed back through the SCI transmitter.
3.4.8
Reserved (Mode 7)
This mode is reserved for future definition. If selected, the processor defaults to Mode 6.
3.5
DSP56002 INTERRUPT PRIORITY REGISTER
Section 7 of the
DSP56000 Family Manual
describes interrupt (exception) processing in
detail. It discusses interrupt sources, interrupt types, and interrupt priority levels (IPL).
Interrupt priority levels for each on-chip peripheral device and for each external interrupt
source can be programmed under software control by writing to the interrupt priority reg-
ister. Level 3 interrupts are nonmaskable, and interrupts of levels 0-2 are maskable.
The DSP56002 Interrupt Priority Register (IPR) configuration is shown in Section Fig-
ure 3-4 DSP56002 Interrupt Priority Register (IPR). The starting addresses of interrupt
vectors in the DSP56002 are defined as shown in Section Table 3-4 Interrupt Vectors,
while the relative priorities of exceptions within the same IPL are defined as shown in
Section Table 3-5 Exception Priorities Within an IPL).
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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