FEATURES
1 - 4
INTRODUCTION TO THE DSP56002
MOTOROLA
1.2
FEATURES
DSP56K Central Processing Unit (CPU) Features
•
20 Million Instructions per Second (MIPS) at 40 MHz
•
Single-Cycle 24 x 24 Bit Parallel Multiply-Accumulator
•
Highly Parallel Instruction Set with Unique DSP Addressing Modes
•
Zero Overhead Nested DO Loops
•
Fast Auto-Return Interrupts
•
Fully Static Logic, Operation Frequency Down to DC
•
Very Low-power CMOS Design
•
STOP and WAIT Low-power Standby Modes
DSP56002 Features
•
512 x 24 Program RAM
•
Two 256 x 24 Data RAM
•
Two 256 x 24 Data ROM (Sine and Cosine Tables)
•
Full Speed Memory Expansion Port with 16-bit Address and 24-bit Data Buses
•
Byte-wide Host Interface with DMA Support
•
Synchronous Serial Interface Port
•
Serial Communication Interface (Asynchronous) Port
•
24 General Purpose I/O Pins
•
24-bit Timer/Event Counter
*
•
On-chip Emulator (OnCE
) for Unobtrusive, Full Speed Debugging
•
Optional Program Security Feature Disables Unauthorized Program ROM and
OnCE Access
•
PLL Based Clocking with Wide Input Frequency Range, Wide Range Frequency
Multiplication (1 to 4096) and Power Saving Clock Divider (2
i
, i=0,...,15) to
Reduce Clock Noise
1.3
DSP56K CENTRAL PROCESSING UNIT OVERVIEW
The DSP56K series of 24-bit modular processors is built on a common central processing
unit (CPU). In the expansion area around the CPU, the chip can support various configu-
rations of memory and peripheral modules which may change between series members.
* The first version of the DSP56002 (mask number D41G) did not have the timer/event counter. Later versions of the DSP56002 which have
different mask numbers do have the timer/event counter. This mask number can be found below the part number on each chip.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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