SYNCHRONOUS SERIAL INTERFACE (SSI)
MOTOROLA
PORT C
6 - 113
I/O may be used per frame. In either case, the transfers are periodic. The normal mode is
typically used to transfer data to/from a single device. Network mode is typically used in time
division multiplexed (TDM) networks of codecs or DSPs with multiple words per frame (see
Figure 6-57, which shows two words in a frame with either word-length or bit-length frame
sync). The frame sync shown in Figure 6-55 is the word-length frame sync. A bit-length
frame sync can be chosen by setting FSL1 and FSL0 for the configuration desired.
6.4.7.1.2
Continuous/Gated Clock Selection
The TX and RX clocks may be programmed as either continuous or gated clock signals
by the GCK bit in the CRB. A continuous TX and RX clock is required in applications such
as communicating with some codecs where the clock is used for more than just data
transfer. A gated clock, in which the clock only toggles while data is being transferred, is
useful for many applications and is required for SPI compatibility. The frame sync outputs
may be used as a start conversion signal by some A/D and D/A devices.
Figure 6-58 illustrates the difference between continuous clock and gated clock systems.
A separate frame-sync signal is required in continuous clock systems to delimit the active
clock transitions. Although the word-length frame sync is shown in Figure 6-58, a
bit-length frame sync can be used (see Figure 6-59). In gated clock systems, frame syn-
chronization is inherent in the clock signal; thus a separate sync signal is not required (see
Figure 6-60 and Figure 6-61). The SSI can be programmed to generate frame sync out-
puts in gated clock mode but does not use frame sync inputs.
Input flags (see Figure 6-60 and Figure 6-61) are latched on the negative edge of the first
data bit of a frame. Output flags are valid during the entire frame.
6.4.7.1.3
Synchronous/Asynchronous Operating Modes
The transmit and receive sections of this interface may be synchronous or asynchronous
– i.e., the transmitter and receiver may use common clock and synchronization signals
(synchronous operating mode, see Figure 6-62) or they may have their own separate
clock and sync signals (asynchronous operating mode). The SYN bit in CRB selects syn-
chronous or asynchronous operation. Since the SSI is designed to operate either syn-
chronously or asynchronously, separate receive and transmit interrupts are provided.
Figure 6-63 illustrates the operation of the SYN bit in the CRB. When SYN equals zero, the
SSI TX and RX clocks and frame sync sources are independent. If SYN equals one, the SSI
TX and RX clocks and frame sync come from the same source (either external or internal).
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Freescale Semiconductor, Inc.
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