SYNCHRONOUS SERIAL INTERFACE (SSI)
6 - 120
PORT C
MOTOROLA
tained from external sources. If internally generated, the SSI clock generator is used to
derive bit clock and frame sync signals from the DSP internal system clock. The SSI clock
generator consists of a selectable fixed prescaler and a programmable prescaler for bit
rate clock generation and also a programmable frame-rate divider and a word-length di-
vider for frame-rate sync-signal generation.
Figures Figure 6-64 through Figure 6-67 show the definitions of the SSI pins during each
of the four main operating modes of the SSI I/O interface. Figure 6-64 uses a gated clock
(from either an external source or the internal clock), which means that frame sync is in-
herent in the clock. Since both the transmitter and receiver use the same clock (synchro-
nous configuration), both use the SCK pin. SC0 and SC1 are designated as flags or can
be used as general purpose-parallel I/O. SC2 is not defined if it is an input; SC2 is the
transmit and receive frame sync if it is an output.
Figure 6-65 shows a gated clock (from either an external source or the internal clock), which
means that frame sync is inherent in the clock. Since this configuration is asynchronous, SCK
is the transmitter clock pin (input or output) and SC0 is the receiver clock pin (input or output).
SC1 and SC2 are designated as receive or transmit frame sync, respectively, if they are se-
XMIT DATA
XMIT DATA
ONE FRAME
WORD TRANSFER FATE (=3)
3 WORDS PER FRAME
START OF
FRAME
WORD
WORD
WORD
WORD
SERIAL CLOCK
FRAME SYNC
TRANSMIT DATA
TRANSMITTER EMPTY
INTERNAL INTERRUPTS AND FLAGS
REC DATA
REC DATA
RECEIVE DATA
RECEIVER FULL
INTERNAL INTERRUPTS AND FLAGS
3-STATE
3-STATE
Figure 6-62 Synchronous Communication
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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