SIGNAL DESCRIPTIONS
2 - 4
DSP56002 PIN DESCRIPTIONS
MOTOROLA
example, during reset, all signals are three-stated. Without pull-up resistors, the BR
and WT signals may become active, causing two or more memory chips to try to
simultaneously drive the external bus, which can damage the memory chips. A pull-
up resistor in the 50K-ohm range should be sufficient. Also, for future enhance-
ments, all reserved pins (see Section Figure 2-1) should be left unconnected.
2.2.1.1
Address (A0–A15)
These three-state output pins specify the address for external program and data memory
accesses. To minimize power dissipation, A0–A15 do not change state when external
memory spaces are not being accessed.
2.2.1.2
Data Bus (D0–D23)
These pins provide the bidirectional data bus for external program and data memory ac-
cesses. D0–D23 are in the high-impedance state when the bus grant signal is asserted.
2.2.2
Port A Bus Control
The Port A bus control signals are discussed in the following paragraphs. The bus control
signals provide a means to connect additional bus masters (which may be additional
DSPs, microprocessors, direct memory access (DMA) controllers, etc.) through port A to
the DSP56002. They are three-stated during reset and may require pull-up resistors to
prevent erroneous operation.
2.2.2.1
Program Memory Select (PS)
This three-state output is asserted only when external program memory is referenced
(see Table 2-1).
PS
DS
X/Y
External Memory Reference
1
1
1
No Activity
1
0
1
X Data Memory on Data Bus
1
0
0
Y Data Memory on Data Bus
0
1
1
Program Memory on Data Bus (Not Exception)
0
1
0
External Exception Fetch: Vector or 1
(Development Mode Only)
0
0
X
Reserved
1
1
0
Reserved
Table 2-1 Program and Data Memory Select Encoding
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Freescale Semiconductor, Inc.
For More Information On This Product,
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