TIMER/EVENT COUNTER MODES OF OPERATION
7 - 8
DSP56002 TIMER AND EVENT COUNTER
MOTOROLA
with the timer enabled. Figure 7-4 illustrates the events with the timer disabled.
Note:
It is recommended that the GPIO input function of Mode 0 only be activated with
the timer disabled. If the processor attempts to read the DI bit to determine the
GPIO pin direction, it must read the entire TCSR register, which would clear the TS
bit and, thus, clear a pending timer interrupt.
7.5.2
Timer Mode 1 (Standard Timer Mode, Internal Clock, Output Pulse Enabled)
Timer Mode 1 is defined by TC2-TC0 equal to 001.
With the timer enabled (TE=1), the counter is loaded with the value contained by the TCR. The
counter is decremented by a clock derived from the DSP’s internal clock, divided by two (CLK/2).
During the clock cycle following the point where the counter reaches 0, the TS bit is set and
the timer generates an interrupt. A pulse with a two clock cycle width and whose polarity is
determined by the INV bit, will be put out on the TIO pin. The counter is reloaded with the
TE
TCR
Write Preload (N)
N
Counter
N
0
N
TS
First Event
Last Event
N-1
Clock (CLK/2)
Interrupt
Figure 7-3 Standard Timer Mode (Mode 0)
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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