Emerson ATCA-8310, Manual

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Functional Description
ATCA-8310 Installation and Use (6806800M72D)
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When an EMAC Rx interrupt happens, the bootloader processes the received packet and passes
the boot tables into memory. As a result of Efusing, the MAC address is stored in registers
0x02A8 0700 and 0x02A8 0704. When the end of the boot table is reached, it clears the Rx
Channel 0 head description pointer to disable reception and exit boots, and jumps to
application.
The Ethernet peripheral is configured to accept a combination of a single MAC address and
broadcast packets, as defined by the Ethernet boot parameter table. The peripheral rejects
packets not matching the MAC addresses selected without a record of the drop.
4.4.2 DSP Memory
The TCI6486 DDR2 interface supports JEDEC DDR2 x16 devices. Supported densities are
256Mb, 512Mb, and 1Gb in the x16 device width. Any JEDEC DDR2-533 speed grade device at
these densities in the x16 width will work with TCI6486's DDR2 controller at 266 MHz clock
speed/533M data rate. The DSP memory on the ATCA-8310 is realized with two DDR2x16
devices per DSP and runs with 266 MHz. The memory access will be 32 bits wide.
4.4.3 DSP TSIP Interface
The TSIP is a multi-link serial interface consisting of a maximum of eight transmit data signals
(or links), eight receive data signals (or links), two frame sync input signals, and two serial clock
inputs. The TSIP module offers support for a maximum of 1024 timeslots for transmit and
receive. Typically, 672 timeslots (DS3) for transmit and receive are utilized on these links. The
TSIP module can be configured to use the frame sync signals and the serial clocks as redundant
sources for all transmit and receive data signals or one frame sync and serial clock for transmit
and the second frame sync and clock for receive. The standard serial data rate for each TSIP
transmit and receive data signal is 8.192 Mbps. The standard frame sync is a one- (or more) bit
wide pulse that occurs once every 125 ms or a minimum of one serial clock period every 1024
serial clocks. At the standard rate and default configuration there are 8 transmit and 8 receive
links that are active. Each serial interface link supports up to 128 8-bit timeslots. This
corresponds to an HMVIP or H.110 serial data rate interface.
The serial interface clock frequency may be either 16.384 MHz (default). Typical timeslot
occupation is 96 timeslots (DS2) for each serial interface link. Seven transmit data links and
seven receive data links are utilized to support the DS3 timeslot requirement. The eighth
transmit and receive links are available to support common channel signaling (CCS).