CHAPTER 4 IMAGE PROCESSING SYSTEM
4-2
COPYRIGHT © 2002 CANON INC. CANON CLC1100/1130/1150/1160/1180 REV.0 MAR. 1999 PRINTED IN JAPAN (IMPRIME AU JAPON)
II.
CCD/CCD DRIVE
A. Controlling the CCD
Table 4-201 shows the major specifications of the CCD.
Item
Specifications
Number of CCD lines
3 lines (GBR)
Number of CCD pixels
5000 pixels/line
Output system
2 channels (odd-/even-number)
Table 4-201
B. CCD Driver Circuit
The CCD driver reduces the impedance of image signals from CCD in its buffer (impedance
reduction circuit), and sends the result to the analog processor PCB.
Figure 4-201
B
G
R
OSAG
CCD
OSBG
OSAB
OSBB
OSAG
OSBG
G-ODD
G-EVEN
B-ODD
B-EVEN
R-ODD
R-EVEN
CCD driver PCB
Buffer
(impedance
reduction circuit)
Clock pulses, shift pulses
Analog processor
PCB
Reference
pulse generation
circuit
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