AMD 3200 - Athlon 64 2.0 GHz Processor Manual Download

Page: 1 / 91

Revision

Guide

for

AMD

Family

Models

Processors

Publication # 48063 Revision: 3.18
Issue Date: October 2012

Advanced

Micro

Devices

Summary of Contents for 3200 - Athlon 64 2.0 GHz Processor

Page 1: ...Revision Guide for AMD Family 15h Models 00h 0Fh Processors Publication 48063 Revision 3 18 Issue Date October 2012 Advanced Micro Devices...

Page 2: ...other applications intended to support or sustain life or in any other application in which the failure of AMD s product could create a situation where personal injury death or severe property or envi...

Page 3: ...List of Figures Figure 1 Format of CPUID Fn0000_0001_EAX 9 48063 Rev 3 18 October 2012 Revision Guide for AMD Family 15h Models 00h 0Fh Processors List of Figures 3...

Page 4: ...r AMD Family 15h Models 00h 0Fh AM3r2 Processor Revisions 10 Table 5 Supported Mixed Revision Configurations 11 Table 6 Cross Reference of Product Revision to OSVW ID 13 Table 7 Cross Reference of Pro...

Page 5: ...Work around MSR1 OSVW_Status section for errata 724 Added errata 691 709 714 717 720 724 726 Removed erratum 534 as this is redundant with and replaced by errata 717 and 718 Changed Fix Planned to Ye...

Page 6: ...nd display the processor name string Product Errata provides a detailed description of product errata including potential effects on system operation and suggested workarounds An erratum is defined as...

Page 7: ...iguration Select DctCfgSel D18F1x10C 0 DZFYxXXX_xZZZZZ Port access through the PCI defined configuration space at bus 0 Z specifies the PCI device address in hex XXX specifies the byte address of the...

Page 8: ...late 3 0 Bitwise OR operator E g 01b 10b 11b Logical OR operator E g 01b 10b 1b logical treats multibit operand as 1 if 1 and produces a 1 bit result Bitwise AND operator E g 01b 10b 00b Logical AND o...

Page 9: ...8F4x164 Fixed Errata Register see D18F4x164 Fixed Errata Register Figure 1 Format of CPUID Fn0000_0001_EAX The following tables show the identification numbers from CPUID Fn0000_0001_EAX and D18F4x164...

Page 10: ...that BIOS or system software can determine the necessity of applying the workaround Under these circumstances the erratum workaround references the specified bit to enable software to test for the pr...

Page 11: ...o not program the proper processor name string and model number will not pass AMD validation and will not be posted on the AMD Recommended Motherboard Web site The name string must be ASCII NUL termin...

Page 12: ...8_x6 and write this value to MSRC001_0033 6 Read D18F5x198_x9 D18F5x198_x8 and write this value to MSRC001_0034 7 Read D18F5x198_xB D18F5x198_xA and write this value to MSRC001_0035 Revision Guide for...

Page 13: ...tem software should use MSRC001_0140 to determine the valid length of the bit status field For all valid status bits 1 Hardware contains the erratum and an OS software work around is required or may b...

Page 14: ...ned 505 Scrub Rate Control Register Address Depends on DctCfgSel No fix planned 520 Some Lightweight Profiling Counters Stop Counting When Instruction Based Sampling is Enabled X 535 Lightweight Profi...

Page 15: ...t X 660 APERF May Increase Unpredictably X 661 P State Limit and Stop Clock Assertion May Cause System Hang No fix planned 663 Local Interrupts LINT0 LINT1 May Occur While APIC is Software Disabled No...

Page 16: ...t No fix planned 717 Instruction Based Sampling May Be Inaccurate X 718 Instruction Based Sampling May Be Inaccurate No fix planned 719 Instruction Based Sampling Fetch Counter Always Starts at Maximu...

Page 17: ...0001_EAX D18F4x164 1 0 00600F12h 01b OR B2 00600F20h 11b OR C0 745 Processor May Incorrectly Report Cache Sharing Property in CPUID Topology X 759 One Core May Observe a Time Stamp Counter Skew X 4806...

Page 18: ...sion s not being used in this package Table 8 Cross Reference of Errata to Package Type Errata Package AM3r2 C32r1 G34r1 361 X X X 503 X X X 504 X X X 505 X X X 520 X X X 535 X X X 536 X X X 537 X X X...

Page 19: ...0 X X X 691 X 693 X X X 694 X X X 695 X X X 699 X X X 704 X X X 707 X X X 708 X X X 709 X X X 714 X X X 717 X X X 718 X X X 719 X X X 720 X X X 724 X X X 725 X X X 726 X X X 727 X X X 734 X X X 737 X...

Page 20: ...rence of Errata to Package Type continued Errata Package AM3r2 C32r1 G34r1 759 X X X Revision Guide for AMD Family 15h Models 00h 0Fh Processors 48063 Rev 3 18 October 2012 20 Cross Reference of Errat...

Page 21: ...ent AMD FX Series Processor AMD Opteron 3200 Processor AMD Opteron 3300 Processor AMD Opteron 4200 Processor AMD Opteron 4300 Processor AMD Opteron 6200 Processor AMD Opteron 6300 Processor 361 X X X...

Page 22: ...663 X X X X X X X 667 X X X X X X X 668 X X X X 671 X X X X 672 X X X X 673 X X X X 674 X X X X 675 X X X X 685 X X X X 689 X 690 X X X X X X X 691 X 693 X X X X X X X 694 X X X X X X X 695 X X X X X...

Page 23: ...teron 4200 Processor AMD Opteron 4300 Processor AMD Opteron 6200 Processor AMD Opteron 6300 Processor 726 X X X X X X X 727 X X X X 734 X X X X 737 X X X X X X X 739 X X X X 740 X X X X X X X 742 X X...

Page 24: ...n instruction with an interrupt shadow and The instruction that generated the exception is immediately followed by an instruction resulting in VMEXIT Potential Effect on System None expected under nor...

Page 25: ...ay use an incorrect internal buffer for the data Potential Effect on System Incorrect interrupt prioritization Suggested Workaround BIOS should set MSRC001_102A 11 to 1b Fix Planned No fix planned 480...

Page 26: ...conditions that involves corrected L3 errors a processor read from the L3 cache may hang Potential Effect on System System hang Suggested Workaround BIOS should program D18F3x1B8 18 to 1b Fix Planned...

Page 27: ...should clear DctCfgSel D18F1x10C 0 to 0b prior to any access to D18F3x58 Scrub Rate Control Register The software must serialize any accesses to D18F3x58 with other accesses to registers that use Dct...

Page 28: ...d 2 Branches retired event counter LWP EventId 3 LWP is enabled once software executes a LLWCP or XRSTOR instruction with a valid LWPCB address IBS instruction execution sampling is enabled when IBS E...

Page 29: ...ed branch a compare operation followed by a conditional branch that is executed as a single operation internally and a PF or nested paging exception occurs during the storing of the event Potential Ef...

Page 30: ...due to sequential prefetches Potential Effect on System Performance monitoring software may undercount instruction cache misses Suggested Workaround Performance monitoring software may use the differ...

Page 31: ...prefetch due to an L2 cache hit does not increment Potential Effect on System Performance monitoring software can not determine ineffective software prefetches due to an L2 cache hit Suggested Workaro...

Page 32: ...instructions may cause this performance monitor to undercount FCOMI FCOMIP F2XM1 Potential Effect on System Performance monitoring software will not have an accurate count of retired micro ops The per...

Page 33: ...that initializes the GART Table Base Address D18F3x98 should set GART Aperture Control DisGartTblWlkPrb D18F3x90 6 1b The GART tables should be in UC DRAM or be updated only using strongly ordered un...

Page 34: ...Performance monitoring software cannot accurately measure latency events The reported latency may greatly exceed the actual latency in some instances Suggested Workaround No workaround is recommended...

Page 35: ...uggested Workaround If WrDatGrossDly D18F2x9C_x0000_0 3 0 0 3 1 _dct 1 0 for all byte lanes including the ECC byte lane and all populated DIMMs 111b BIOS should set DataTxFifoWrDly D18F2x210_dct 1 0 _...

Page 36: ...em shutdown The extended error code logged in the IF Machine Check Status register indicates a decode instruction buffer error MSR0000_0405 20 16 10010b Potential Effect on System Machine check except...

Page 37: ...n of this the processor does not signal UD exception for AVX instructions VPEXTRQ and VPINSRQ when VEX W 1 and the processor is running in 32 bit legacy or compatibility modes Instead the instruction...

Page 38: ...check exception for a branch status register parity error simultaneous to the above error MC1_STATUS ErrorCodeExt MSR0000_0405 20 16 00110b identifies a branch status register parity error Suggested W...

Page 39: ...RC error detected on an unrelated read packet This error can only occur on a coherent HyperTransport link Potential Effect on System System hang Suggested Workaround BIOS should not alter D18F0x150 11...

Page 40: ...ecific to each Gen3 frequency and may be programmed only while the link is operating at a Gen1 frequency less than or equal to 2 0 GT s Potential Effect on System System hang Suggested Workaround Soft...

Page 41: ...processor P state capabilities may not be notified of all P state limit changes resulting in either one of the following conditions The processor runs continuously in a lower performance higher number...

Page 42: ...indefinitely on non posted reads when a posted write becomes dependent on probe responses Potential Effect on System System hang Suggested Workaround BIOS should set D18F5x88 14 1b Fix Planned Yes Re...

Page 43: ...eption even when no limit violation exists Potential Effect on System None expected In the unlikely case that a code segment is 32 bytes or smaller an unexpected GP exception may occur Suggested Worka...

Page 44: ...e disabled Control Register TimeoutDis SBRMI_x01 2 the SB RMI processor state accesses will not receive a successful completion instead of a command timeout Potential Effect on System Under rare circu...

Page 45: ...uires that message triggered C1E is enabled D18F3xD4 13 1b Clock Power Timing Control 0 MTC1eEn The functionality of the SB RMI interface is not otherwise affected Potential Effect on System Software...

Page 46: ...0000_7FFF_FFFF_FFFFh 0000_7FFF_FFFF_FFF2h and multiple branch mis predicts occur to a linear memory address at the limit of canonical address space Potential Effect on System In the unlikely event tha...

Page 47: ...tep This is the node that reported the machine check 2 DramLimitSysAddrReg D 18h NodeReportingMca F1x124 where 18h NodeReportingMca is the device number of the node that reported the machine check In...

Page 48: ...ess TempMcaAddress MC4_ADDR 11 0 In this step the low order bits of the machine check address are placed into the calculated address e The physical DRAM address of the machine check error is Cc6BaseAd...

Page 49: ...s that are affected by this erratum when it observes an MC1_STATUS register with all of the following MC1_STATUS Valid bit 63 1b MC1_STATUS Uc bit 61 0b MC1_STATUS En bit 60 0b MC1_STATUS Pcc bit 57 0...

Page 50: ...one expected Suggested Workaround Software may substitute the following values to determine the number and associativity of large page L2 TLB entries CPUID Fn8000_0006_EAX L2ITlb2and4MSize 1024 CPUID...

Page 51: ...dow This erratum does not occur on the last iteration of the Move String instruction Potential Effect on System The SVM guest may continue to operate under interrupt shadow until the Move String instr...

Page 52: ...HTC application power management APM or advanced platform management link APML TDP limiting Execution of the MWAIT instruction Potential Effect on System Software may calculate the effective frequency...

Page 53: ...refresh mode for an S3 sleep state transition or a system hang if it occurs while another processor core is transitioning to the Core C6 CC6 state Potential Effect on System System hang Suggested Work...

Page 54: ...y by setting Link Transaction Control Register LintEn D18F0x68 16 1b If this bit is set while the APIC is software disabled an ExtInt or NMI interrupt causes an unexpected local interrupt Potential Ef...

Page 55: ...t changes due to SB RMI software or HTC as well as to generate interrupts for changes to TDP Limit 3 Register ApmTdpLimit D18F5xE8 28 16 Potential Effect on System Operating systems monitoring process...

Page 56: ...on Status FSW ES bit 7 is already 1b Potential Effect on System None expected Operating systems typically set CR0 NE 1b or floating point exception handlers normally clear the exception status FSW ES...

Page 57: ...your AMD representative for information on a BIOS update This workaround has a performance impact when certain debug breakpoints are enabled System developers that wish to enable debug breakpoints wit...

Page 58: ...01b MSRC001_020 A 8 6 4 2 0 41 40 and EFER SVME 1b MSRC000_0080 12 Potential Effect on System Performance monitoring software overcounts events for an SVM guest when non intercepted SMIs occur Suggest...

Page 59: ...le the string operation is executing or the trailing page of the string operation crosses into a large page 1 GB or 2 MB which requires an address translation due to a TLB miss Potential Effect on Sys...

Page 60: ...his can only occur if a prefetch operation persists through the invalidation or flushing of TLB entries and cache lines before the remapped memory region is accessible in a coherent manner There have...

Page 61: ...erved unless the operating system s page fault handler has some dependency on this interim processor state which is not the case in any known operating system software The interim state does not impac...

Page 62: ...0 ApicId is odd i e bit 24 is 1b as compared to when the performance counter is used on an even processor core number Potential Effect on System Performance monitoring software may not have an accurat...

Page 63: ...ements an option to disable CC6 the system may experience low performance in this mode Suggested Workaround AMD recommends that CC6 is enabled This erratum does not apply in this case and no workaroun...

Page 64: ...g to a hang of both cores of a compute unit The processor may also report a probe filter protocol machine check exception identified by the extended error code in the NB Machine Check Status Register...

Page 65: ...e and is configured using at least one 1 MB L3 subcache as indicated by the L3SubcacheSize fields L3 Cache Parameter Register L3SubcacheSize 3 0 D18F3x1C4 15 12 11 8 7 4 3 0 Dh or Eh Potential Effect...

Page 66: ...ding the MXCSR register PMCx003 Retired Floating Point Ops Potential Effect on System Performance monitoring software will not have an accurate count of the number of retired floating point operations...

Page 67: ...on System Performance monitoring software may not receive even unbiased IBS sampling of the instruction fetch stream However IBS can still be used effectively for identifying performance issues assoc...

Page 68: ...ecuting an FNSAVE or FSAVE instruction is unusual and AMD has not observed the above conditions in any commercially available software In the unlikely event that software creates the conditions descri...

Page 69: ...ommended BIOS settings The machine check has the following signature The MC4_STAT register MSR0000_0411 is equal to BA000020_000B0C0F Bit 62 error overflow or bit 59 miscellaneous valid of MC4_STAT ma...

Page 70: ...correct instruction pointer rIP while processing an interrupt or a debug trap exception DB Potential Effect on System Unpredictable system behavior Suggested Workaround Contact your AMD representative...

Page 71: ...ocked operations Potential Effect on System Performance monitoring software may receive an incorrect larger count of the number of cycles spent in the non speculative phase of locked operations Sugges...

Page 72: ...ue to a P state limit change or a software initiated P state change any halt instruction or C state activity the above initial offset error is removed It is possible that the BIOS could observe the TS...

Page 73: ...processor reset occurs P state limit changes that may cause this erratum may be due to SB RMI SBI P state Limit PstateLimit MSRC001_0072 10 8 software Software P state Limit Register SwPstateLimit D1...

Page 74: ...eset This may be observed as a system hang The machine check has the following signature The MC4_STAT register MSR0000_0411 is equal to BA000020_000B0C0F Bit 62 error overflow or bit 59 miscellaneous...

Page 75: ...In rare instances a tagged branch may set an inaccurate value in IBS Branch Target Address Register MSRC001_103B Potential Effect on System Inaccuracies in performance monitoring software may be expe...

Page 76: ...IbsFetchEn MSRC001_1030 48 1b are enabled simultaneously valid execution sample data may be overwritten by a fetch sample resulting in IBS data that is inconsistent with the accompanying IBS executio...

Page 77: ...30 19 4 Potential Effect on System System software that is managing multiple processes or virtual machines with different IBS configurations may create unintended delays before the next IBS sample by...

Page 78: ...rare circumstances a debug exception may occur in an interrupt shadow Under common software use this exception does not have a system effect In the event that system software uses STI RET instead of a...

Page 79: ...411 is equal to BA000020_000B0C0F Bit 62 error overflow or bit 59 miscellaneous valid of MC4_STAT may or may not be set Bits 5 1 of the MC4_ADDR register MSR0000_0412 is equal to one of 10011b 10100b...

Page 80: ...read status field APIC300 17 16 This erratum does not impact the use of remote APIC reads by BIOS during early power on self test POST when the remote read is performed for addresses APIC300 APIC3F0 P...

Page 81: ...ll bytes of an unaligned load instruction that crosses a cache line boundary 64 bytes the processor may intermittently report the address of the unaffected cache line in MC0_ADDR MSR0000_0402 Potentia...

Page 82: ...e the processor may hang Potential Effect on System Processor core hang usually resulting in a system hang Suggested Workaround BIOS should set MSRC001_1000 15 1b Fix Planned No fix planned Revision G...

Page 83: ...processor may store incorrect data to the virtual machine control block VMCB reserved and guest save areas and may also store outside of the VMCB Potential Effect on System Data corruption Suggested W...

Page 84: ...t canonical for all eight bytes of the operation Therefore this erratum can only occur if the segment register is non zero and causes a wrap in the logical address space only In the unlikely event tha...

Page 85: ...processor does not actually use the contents of this branch status register however it may report a parity error machine check exception MC Potential Effect on System The processor reports an uncorrec...

Page 86: ...ed for an LWP event record to be stored Only LWP record type 2 instructions retired or LWP record type 3 branches retired events can cause this hang to occur LWP is enabled once software executes an L...

Page 87: ...eads of the memory attached to the affected DRAM controller return unpredictable data The processor may report but not necessarily in all circumstances an uncorrectable DRAM ECC machine check error Th...

Page 88: ...are set to zero when the processor resumes from CC6 state This erratum only applies on processor models that have a single core per compute unit Compute Unit Status Register DualCore D18F5x80 16 is 0b...

Page 89: ...and the L2 cache as being shared between two processor cores On the above mentioned processor models the instruction cache and the L2 cache are not shared and software would not find two processor co...

Page 90: ...hread or processor core provides TSC values that are behind all of the other threads or processor cores While a single thread operating on a single core can not observe successively stored TSC values...

Page 91: ...em Instructions order 24594 AMD64 Architecture Programmer s Manual Volume 4 128 Bit and 256 Bit Media Instructions order 26568 AMD64 Architecture Programmer s Manual Volume 5 64 Bit Media and x87 Floa...

Search results

Summary of Contents for 3200 - Athlon 64 2.0 GHz Processor

Reviews:

Related manuals for 3200 - Athlon 64 2.0 GHz Processor

Brands by name

Popular brands

AMD 3200 - Athlon 64 2.0 GHz Processor, Manual

Search results

Summary of Contents for 3200 - Athlon 64 2.0 GHz Processor

Reviews:

Related manuals for 3200 - Athlon 64 2.0 GHz Processor

Brands by name

Popular brands