Agilent Technologies J-BERT N4903, User Manual

Page: 91 / 434

N O T E
If the Divider Factor n is uneven (e.g. 3), the clock's duty cycle will not be 50%, but
the signal will stay high for (n+1)/2 and low for (n-1)/2. This results in a DCD of 0.5
UI.
Bit Rate - Reference
The Bit Rate Setup window contains the following elements:
Clock Source
Clock source can be one of the following:
•
Internal: The clock generator uses the internal oscillator.
•
10 MHz Ref: The clock generator uses the 10 MHz Reference that must
be connected to the 10 MHz Ref Input.
•
External: The pattern generator uses the external clock that must be
connected to the Clock Input. You can choose between
“Automatic
and Manual Mode” on page 91 .
•
External PLL: The pattern generator uses the external clock that
must be connected to the Clock Input. This clock is routed internally
through a PLL. You can choose between
“Automatic and Manual
Mode” on page 91 .
Automatic and Manual Mode
The Manual checkbox is available if you have chosen an external clock
source.
In automatic mode, the external clock frequency is continually
measured. When the external clock frequency changes, the bit rate
changes as well.
In manual mode, you can enter the expected frequency or press the
Measure & Set button. Measure & Set requires that the external clock
generator is connected and active. Its frequency is measured once and
determines the bit rate. When the external clock frequency changes,
PG
Clock Loss is signaled.
Setting up the Pattern Generator
3
Agilent J-BERT N4903 High-Performance Serial BERT 91