6-2
IM 704510-01E
Explanation
Selecting the Gate Mode
Select the gate mode that defines the gate (range of the measurement block) from the
following:
• Event (event size)
Set the event size within the following range (resolution: 1). However, when block
sampling (Block) is ON and the rest time (RestMode) is set to RestTime or RestEvent,
the resolution is 2.
• Time stamp mode or inter-symbol interference analysis mode
• Single measurement function: 2 to 1024000
• Dual measurement function:
1 to 512000
• Hardware histogram mode
• Single measurement function: 2 to 10
9
• Dual measurement function:
1 to 10
9
• Time (gate time)
Set the gate time within the following range (resolution: 100 ns).
1
µ
s
≤
gate time
≤
10 s
• External
(external gate input)
Select the input signal polarity from the following:
•
: Measurement is performed while a positive polarity signal is being applied to
the external gate input terminal (EXT ARM/EXT GATE).
•
: Measurement is performed while a negative polarity signal is being applied to
the external gate input terminal (EXT ARM/EXT GATE).
Note
•
The measurement of a single block is terminated when the time from arming reaches the
maximum sampling time before the specified event size is reached.
•
The measurement of a single block is terminated when the event size of a single block reaches
the maximum event size of the sampling mode before the specified gate time elapses.
•
The measurement of a single block is terminated when the maximum sampling size of the
sampling mode is reached or when the maximum sampling time elapses even if the external
gate remains open for an extended time.
•
Block sampling is turned OFF when external gate is selected. In addition, arming is set to Auto.
Input Method of the External Gate Signal
Apply a signal to the terminal marked EXT ARM/EXT GATE on the front panel (the
terminal is shared with the external arming) according to the following specifications.
• Input impedance:
1 M
Ω
(typical value*)
• Input coupling:
DC
• Gate level:
Using the above procedure, select 0 V, TTL (1.4 V), or
TTL/10 (0.14 V).
• Maximum input voltage:
40 V (DC+ACpeak)
• Minimum input pulse width: 30 ns
• Setup time:
60 ns (must precede the measurement signal by at least
50 ns for the gate to be valid).
• Allowable gate open time:
1
µ
s to 320 s (except within the maximum sampling size
of the sampling mode)
*
Typical value represents a typical or average value. It is not strictly warranted.
CAUTION
Applying a voltage that exceeds the maximum input voltage indicated above to the
external gate input terminal can damage the instrument.
6.1 Setting the Gate