Preliminary
PRODUCT OVERVIEW
S3C2451X RISC MICROPROCESSOR
1-2
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
FEATURES
Architecture
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Integrated system for hand-held devices and
general embedded applications.
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16/32-Bit RISC architecture and powerful
instruction set with ARM926EJ CPU core.
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Enhanced ARM architecture MMU to support
WinCE, EPOC 32 and Linux.
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Instruction cache, data cache, write buffer and
Physical address TAG RAM to reduce the effect
of main memory bandwidth and latency on
performance.
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ARM926EJ CPU core supports the ARM debug
architecture.
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Internal Advanced Microcontroller Bus
Architecture (AMBA) (AMBA2.0, AHB/APB).
System Manager
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Little/Big Endian support.
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Two independent memory bus - one for the
ROM/SRAM bus (ROM Bank0~Bank5) and one
for the DRAM bus (mSDR/mDDR/DDR2
SDRAM Bank0~Bank1)
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Address space: 64M bytes for Rom bank0 ~
bank5, 128M bytes for SDRAM bank0 ~ bank1.
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Supports programmable 8/16-bit data bus width
for ROM/SRAM bank and programmable 16/32-
bit data bus width for SDRAM bank
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Fixed bank start address from Rom bank 0 to
bank 5 and SDRAM bank 0 to bank1.
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Eight memory banks:
– Six memory banks for ROM, SRAM, and
others (NAND/CF etc.).
– Two memory banks for Synchronous DRAM.
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Complete Programmable access cycles for all
memory banks.
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Supports external wait signals to expand the bus
cycle.
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Supports self-refresh mode in SDRAM for
power-down.
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Supports various types of ROM for booting
(NOR/NAND Flash, EEPROM, OneNAND and
others).
NAND Flash Boot Loader
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Supports booting from NAND flash memory.
(Only 8bit boot support)
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64KB for internal SRAM Buffer(8KB internal
buffer for booting)
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Supports storage memory for NAND flash
memory after booting.
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Supports Advanced NAND flash
Cache Memory
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64-way set-associative cache with I-Cache
(16KB) and D-Cache (16KB).
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8words length per line with one valid bit and two
dirty bits per line.
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Pseudo random or round robin replacement
algorithm.
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Write-through or write-back cache operation to
update the main memory.
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The write buffer can hold 16 words of data and
four addresses.
Clock & Power Manager
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On-chip MPLL and EPLL:
EPLL generates the clock to operate USB Host,
IIS, UART, etc.
MPLL generates the clock to operate MCU at
maximum 533MHz @ TBD V.
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Clock can be fed selectively to each function
block by software.
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Power mode: Normal, Idle, Stop, Deep Stop and
Sleep mode
Normal mode: Normal operating mode
Idle mode: The clock for only CPU is stopped.
Stop mode: All clocks are stopped.
Deep Stop mode: CPU power is gated and all
clocks are stopped.
Sleep mode: The Core power including all
peripherals is shut down.
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Woken up by EINT[15:0] or RTC alarm & tick
interrupt from (Deep)Sleep mode and STOP
mode.
